3DIC Package Layout for Heat Dissipation Without Top-Die Through-Vias

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Solution Overview

Problem

Current die-to-wafer and wafer-to-wafer bonding techniques face challenges in effectively dissipating heat generated by top dies, leading to potential damage to bottom dies and limitations in active region space for top dies due to the presence of through-vias in both dies.

Innovation Solution

The method involves face-to-face bonding of top dies to a bottom wafer with formed through-vias, encapsulating top dies in a gap-filling material, and forming a backside interconnect structure on the bottom wafer to dissipate heat through a supporting substrate, eliminating through-vias in top dies and optimizing active region space.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If through-vias are formed in both top dies and bottom dies for heat dissipation, then heat dissipation capability is improved, but active region space for top dies is reduced

Engineering Contradiction:
Improveheat dissipation capabilityVSAvoidactive region space
Core Design Contradiction:
TemperatureVSArea of stationary object

Solution Approach 1:

The invention extracts the through-vias from the top dies and relocates them exclusively to the bottom dies. This separation allows the top dies to maintain their full active region space while the bottom dies handle all the through-vias for heat dissipation and electrical connection functions.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The invention moves the heat dissipation function from a vertical dimension (through-vias penetrating top dies) to a horizontal dimension (backside interconnect structures on bottom wafer), thereby preserving the active region space on top dies while maintaining heat dissipation capability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Temperature

If through-vias are formed in top dies, then heat dissipation path is created, but manufacturing complexity increases

Engineering Contradiction:
Improveheat dissipation pathVSAvoidmanufacturing complexity
Core Design Contradiction:
TemperatureVSDevice complexity

Solution Approach 1:

The invention extracts the through-via formation process from the top die fabrication sequence and consolidates it into the bottom wafer processing sequence, thereby reducing the manufacturing complexity of top dies while maintaining heat dissipation functionality.

Inventive Principle:
Principle #2Taking out (Extraction)

3Productivity

If face-to-face bonding is used to bond top dies to bottom wafer, then packaging density is improved, but heat dissipation efficiency deteriorates

Engineering Contradiction:
Improvepackaging densityVSAvoidheat dissipation efficiency
Core Design Contradiction:
ProductivityVSTemperature

Solution Approach 1:

The invention shifts heat dissipation from a vertical conduction path through bonded interfaces to a lateral conduction path through the bottom wafer substrate, enabling effective heat management while preserving the space-efficient face-to-face bonding configuration.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively dissipates heat generated by top dies, reduces damage to bottom dies, and increases the active region space for top dies by using the supporting substrate as a heat sink, while also allowing for more through-vias in the bottom die, enhancing packaging efficiency and performance.

Implementation Method 1

the heat generated in the top die(s) may be effectively dissipated through the supporting substrate

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

using the supporting substrate as a heat sink

Methodology Applied
Scientific EffectHeat sink: Heat Sink

Data Source

PatentUS20240072034A13DIC Package and Method Forming the Same
Publication Date: 2024.02.29 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240072034A1 patent drawing
  • US20240072034A1 patent drawing
  • US20240072034A1 patent drawing

AI summary

A method includes bonding a first device die to a second device die through face-to-face bonding, wherein the second device die is in a device wafer, forming a gap-filling region to encircle the first device die, performing a backside-grinding process on the device wafer to reveal a through-via in the second device die, and forming a redistribution structure on the backside of the device wafer. The redistribution structure is electrically connected to the first device die through the through-via in the second device die. A supporting substrate is bonded to the first device die.