3DIC Package Thermal Structure Using RDLs and Connectors
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Solution Overview
Problem
Existing 3DIC packages have a large form factor, require complex heat dissipation features, and costly interconnect structures like TSVs, which result in long conduction paths and increased manufacturing costs.
Innovation Solution
A semiconductor package design featuring a die stack with redistribution layers (RDLs) and connectors on the same surface, allowing for a small form factor, reduced conduction paths, and independent heat dissipation features on opposite surfaces of the dies, eliminating the need for through-substrate vias and simplifying heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-substrate vias (TSVs) are used for interconnect structures, then electrical connection between dies is achieved, but manufacturing cost increases and conduction path length increases
Solution Approach 1:
The interconnect structure is segmented into multiple functional layers: redistribution layers (RDLs) for signal routing, connectors for electrical bonding, and heat dissipation features for thermal management. This segmentation eliminates the need for through-substrate vias while maintaining electrical connectivity between dies through alternative pathways using RDLs and connector arrays.
Solution Approach 2:
The patent transitions from vertical through-substrate via connections to a combination of planar redistribution layers and connector arrays. By distributing connections across multiple dimensions (planar RDL networks combined with vertical connector arrays), the design achieves electrical connectivity without requiring deep through-substrate vias, thereby reducing manufacturing complexity and cost.
2Reliability
If through-substrate vias (TSVs) are used for interconnect structures, then electrical connection between dies is achieved, but conduction path length increases
Solution Approach 1:
The conduction path is segmented into multiple short segments through the use of redistribution layers and connector arrays, replacing the single long path through TSVs. Each RDL layer provides localized signal routing, and connectors establish direct electrical bonds between dies, creating multiple shorter conduction pathways that reduce overall path length and improve signal integrity.
3Temperature
If complex heat dissipation features are used, then heat dissipation efficiency is improved, but device complexity increases
Solution Approach 1:
The patent merges heat dissipation functionality with the existing interconnect structure by integrating heat dissipation features directly into the package substrate and die assembly. Rather than adding separate complex heat dissipation systems, the design combines thermal management functions with the structural components already present in the 3DIC package, thereby improving heat dissipation without proportionally increasing device complexity.
4Reliability
If bonded die stack with traditional interconnects is used, then 3DIC functionality is achieved, but form factor increases
Solution Approach 1:
The patent utilizes vertical stacking of dies combined with planar redistribution layers to achieve high-density interconnectivity in a compact footprint. By organizing connections in three dimensions (vertical die stacking with lateral RDL routing), the design maintains full 3DIC functionality while minimizing the planar form factor, as signals are routed through multiple layers rather than requiring large lateral distances.
Data Source
AI summary
An embodiment device includes a first die, a second die electrically connected to the first die, and a heat dissipation surface on a surface of the second die. The device further includes a package substrate electrically connected to the first die. The package substrate includes a through-hole, and the second die is at least partially disposed in the through hole.