3DIC Package Structure Without Carrier Handling and With Thermal Dies
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Solution Overview
Problem
Current three-dimensional integrated circuit (3DIC) packaging methods face challenges such as high process costs and complexity due to the requirement of a carrier for substrate processing, which increases the time and reduces yield, and lack effective thermal dissipation strategies.
Innovation Solution
A method for forming package structures that involves thinning the substrate after supplying molding material between the chip and dies, eliminating the need for a carrier and incorporating multiple thermal-dissipation dies for enhanced thermal management, with through-silicon via (TSV) structures and bonding films for electrical connectivity and thermal dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a carrier is used for substrate processing in 3DIC packaging, then the substrate can be handled and processed, but the process cost and complexity increase, and the production time is extended
Solution Approach 1:
The patent removes the carrier from the packaging process entirely. The substrate is processed and packaged directly without being mounted on a carrier, eliminating the steps of carrier attachment and carrier removal, thereby simplifying the overall process while maintaining substrate handling capability
Solution Approach 2:
The substrate serves its own handling and processing functions without requiring an external carrier. The packaging process is designed to work directly with the substrate, allowing it to be processed, packaged, and handled in its own right, eliminating the intermediary carrier component
2Ease of manufacture
If a carrier is used for substrate processing in 3DIC packaging, then the substrate can be handled and processed, but the production time is extended and yield is reduced
Solution Approach 1:
By extracting the carrier from the process, the patent eliminates the time-consuming steps of mounting substrates on carriers and subsequently removing carriers after packaging. This direct processing approach significantly reduces cycle time and increases production throughput while maintaining ease of substrate handling
Solution Approach 2:
The patent skips the intermediate carrier-based handling steps entirely, moving directly from substrate processing to packaging. This eliminates unnecessary process steps and accelerates production, improving yield by reducing the time substrates are exposed to potential contamination or damage
3Device complexity
If traditional packaging structures are used, then the packaging process is simple, but thermal dissipation is insufficient
Solution Approach 1:
The packaging structure is segmented into multiple functional layers including the substrate, molding material layer, and thermal dissipation dies. This segmentation allows each layer to perform its specific function optimally, with thermal dissipation dies specifically dedicated to heat management while other layers handle packaging and protection
Solution Approach 2:
The substrate serves multiple functions: it provides mechanical support for mounting the chip and dies, serves as a platform for forming interconnect structures and TSVs, and when combined with thermal dissipation dies, contributes to thermal management. This multi-functionality integrates structural and thermal management roles without significantly increasing overall complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the packaging process, reduces costs and time by eliminating carrier handling, and provides effective thermal dissipation through uniformly distributed thermal-dissipation dies, enhancing the overall performance and reliability of the package structure.
Implementation Method 1
supplying the molding material to a gap between the chip and the dies
Implementation Method 2
bonding a thermal-dissipation die over the first surface of the substrate and adjacent to the chip
Data Source
AI summary
A method for forming a package structure is provided, wherein the method includes forming an interconnect structure in a substrate. The method also includes bonding a chip over the substrate and electrically connected to the interconnect structure. The method includes bonding a plurality of dies over the substrate and adjacent to the chip. The method also includes supplying a molding material to the gap between the chip and the dies, after which the method includes thinning down the substrate.