3DIC Package Structure for Clean TSV Revelation
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Solution Overview
Problem
The increasing complexity of integrated circuit packages, such as System on Integrated Chip (SoIC), which include multiple device dies with different technologies and functions, poses challenges in manufacturing cost and device performance optimization due to the need for effective bonding and protection of encapsulation surfaces during through substrate via (TSV) revelation.
Innovation Solution
A method for forming a 3DIC structure that includes bonding dies to a wafer, encapsulating them, and forming recesses to protect the encapsulation surface from etching, using isolation layers and conductive terminals to reveal TSVs while minimizing contamination and defects, followed by planarization and redistribution layers for electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the encapsulation surface is exposed during TSV revelation, then the TSVs can be accessed for electrical connectivity, but the encapsulation surface is susceptible to etching damage and chamber contamination
Solution Approach 1:
A mask layer is introduced as an intermediary protective element between the etching environment and the encapsulation surface. This mask layer allows TSVs to be revealed and accessed for electrical connectivity while simultaneously protecting the encapsulation surface from etching damage and chamber contamination during the fabrication process
Solution Approach 2:
The mask layer is applied to the encapsulation surface before the TSV revelation process begins. This preliminary protective action ensures that when etching or other potentially harmful processes are performed to access the TSVs, the encapsulation surface is already protected, preventing damage before it can occur
2Adaptability or versatility
If multiple device dies are bonded in the same package to achieve more functions, then the system functionality is enhanced, but the manufacturing complexity and bonding precision requirements increase
Solution Approach 1:
The package structure is segmented into distinct functional regions with separate encapsulation surfaces for different device dies. This segmentation allows each die to be independently processed and bonded, reducing the overall manufacturing complexity while maintaining enhanced system functionality through the integration of multiple specialized components
Solution Approach 2:
The mask layer structure serves multiple functions simultaneously: it protects the encapsulation surface from etching damage, prevents chamber contamination, and enables TSV access for electrical connectivity. This multi-functionality reduces the need for additional separate process steps, thereby managing manufacturing complexity while supporting complex multi-die package configurations
Data Source
AI summary
Packages and methods of fabricating the same are provided. The package includes a first die, wherein the first die includes a plurality of through vias from a first surface of the first die toward a second surface of the first die; a second die disposed below the first die, wherein the second surface of the first die is bonded to the second die; an isolation layer disposed in the first die, wherein the plurality of through vias extend through the isolation layer; an encapsulation laterally surrounding the first die, wherein the encapsulation is laterally separated from the isolation layer; a buffer layer disposed over the first die, the isolation layer, and the encapsulation; and a plurality of conductive terminals disposed over the isolation layer, wherein the plurality of conductive terminals is electrically connected to corresponding ones of the plurality of through vias.