3DIC Conductive Post Formation Without Electroplating Height Variation
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing the turnaround time and cost of forming conductive posts in 3D integrated circuits (3DICs) due to the need for high current electroplating, which leads to height uniformity issues and additional processing steps that can cause stress and cracks in the bump structure.
Innovation Solution
The method involves forming through holes in a molding material using a laser and filling them with a conductive material to create conductive posts that electrically connect the upper and lower semiconductor chip dies, using a via last structure and hybrid bonding to reduce stress and cost, and employing a hardened conductive paste with materials like aluminum or tungsten for the sacrificial pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a higher current per unit area is applied during electroplating to reduce turnaround time, then the turnaround time for forming conductive posts is reduced, but height uniformity of the conductive posts deteriorates
Solution Approach 1:
The patent replaces the electroplating process with a laser-based through-hole drilling process followed by conductive material filling. This substitution eliminates the need for high current electroplating while achieving the same functional result of forming conductive posts, thereby resolving the contradiction between productivity improvement and manufacturing precision deterioration.
Solution Approach 2:
The patent changes the formation method parameter from electroplating (current-driven) to laser drilling and material filling (energy-driven). This parameter change allows for better control of conductive post height uniformity while maintaining or improving turnaround time, as laser processing offers precise control over hole depth and dimensions.
2Manufacturing precision
If additional overmolding and grinding processes are performed to reduce height deviation, then height uniformity is improved, but additional cost occurs and stress and cracks are caused in the bump structure
Solution Approach 1:
The patent replaces the mechanical overmolding and grinding processes with a laser-based through-hole drilling process. This substitution eliminates the need for additional mechanical processing steps while achieving the desired height uniformity, thereby reducing device complexity and avoiding the harmful effects of stress and cracks in the bump structure.
Solution Approach 2:
The patent extracts and removes the problematic additional overmolding and grinding processes from the manufacturing flow. By using laser drilling to directly form through holes with precise depth control, the patent eliminates the need for these separate height-correction steps, simplifying the overall process and avoiding structural damage.
3Reliability
If conventional electroplating is used to form conductive posts, then electrical connection is achieved, but high cost and long turnaround time occur
Solution Approach 1:
The patent substitutes the electroplating process with laser drilling followed by conductive material filling. This replacement maintains the electrical connection function while significantly reducing turnaround time, as laser processing is faster and the material filling step is more efficient than traditional electroplating operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the cost and turnaround time for forming conductive posts while minimizing stress and crack formation in the bump structure, enhancing the reliability and efficiency of the 3D integrated circuit manufacturing process.
Implementation Method 1
forming through holes in a molding material with a laser
Data Source
AI summary
A 3D integrated circuit structure, comprising: a redistribution layer structure; a first semiconductor chip die on the redistribution layer structure; a plurality of sacrificial pads on the redistribution layer structure; a plurality of conductive posts disposed adjacent the first semiconductor chip die, wherein the plurality of conductive posts is on the plurality of sacrificial pads, respectively; a molding material that is on the first semiconductor chip die, the plurality of sacrificial pads, the plurality of conductive posts, and the redistribution layer structure; an interconnection structure on the molding material; and a second semiconductor chip die on the interconnection structure, wherein the second semiconductor chip die overlaps the first semiconductor chip die and the plurality of conductive posts in a vertical direction.