3DIC Die Layout Using Shared Masks and TSV-Based Addressing
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Solution Overview
Problem
The increasing complexity and cost of photomask sets for integrated circuit (IC) designs, particularly due to smaller IC requirements, necessitate a reduction in mask requirements and costs, especially during engineering change orders (ECOs), where existing technologies fail to efficiently utilize redundancy and maintain design efficiency across different IC process technology generations.
Innovation Solution
A design methodology for three-dimensional integrated circuits (3DICs) that allows for identical bit-cell device dice to share the same mask set, utilizing through-silicon vias (TSVs) and multiplexers to enable unique addressing without requiring distinct photomasks, thereby reducing mask requirements and costs by 50% while maintaining design efficiency across different IC process technologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional photomask techniques are used for each unique IC design, then design flexibility and uniqueness are maintained, but mask generation costs increase substantially
Solution Approach 1:
The patent applies universality by designing identical bit-cell device dice that can be uniquely addressed through TSV configurations and multiplexer settings, allowing a single photomask set to fabricate multiple functional devices. This enables one mask set to serve multiple purposes across different device configurations, reducing mask generation costs while maintaining design flexibility through programmable addressing and routing.
2Ease of manufacture
If dummy cells and spare wires are added to minimize new masks for ECOs, then mask costs at chip level are reduced, but redundancy increases packaging level mask requirements
Solution Approach 1:
The patent extracts the addressing and routing functionality from the physical layout of dummy cells and spare wires, implementing it instead through TSV configurations and multiplexer settings. This removes the need for physical redundancy elements while maintaining the capability to perform engineering change orders without requiring additional masks, thereby reducing both chip-level and packaging-level mask requirements.
3Area of moving object
If IC designs are shrunk to increase circuit element density, then area efficiency improves, but mask generation costs increase
Solution Approach 1:
The patent merges multiple device functions into identical bit-cell device dice that share the same photomask set. By combining addressing, routing, and functional logic into unified device structures with programmable TSV and multiplexer configurations, the design achieves high circuit element density while using fewer unique masks, thereby reducing mask generation costs despite advanced process node shrinkage.
Data Source
AI summary
A layout design methodology is provided for a device that includes two or more identical structures. Each device can have a first die, a second die stacked over the first die and a third die stacked over the second die. The second die can include a first through-silicon via (TSV) and a first circuit, and the third die can include a second TSV and a second circuit. The first TSV and the second TSV can be linearly coextensive. The first and second circuit can each be a logic circuit having a comparator and counter used to generate die identifiers. The counters of respective device die can be connected in series between the dice. Each die can be manufactured using the same masks but retain unique logical identifiers. A given die in a stack of dice can thereby be addressed by a single path in a same die layout.