3DIC Die Stack Layout With TDV Routing for High-Bandwidth Links
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high integration density, reduced interconnect lengths, and increased bandwidth in three-dimensional integrated circuits (3DICs) due to limitations in packaging and interconnection methods, particularly in systems on integrated chips (SoICs) and 3DICs, which are overwhelmed by massive data demands in AI and big data applications.
Innovation Solution
The implementation of an interconnection device die with a redistribution layer (RDL) structure and through-silicon via (TSV) structures in a SoIC architecture, allowing for compact designs with enhanced device-to-device connections and high-bandwidth memory, reducing the distance between processors and memories, and incorporating non-TSV dies to optimize manufacturing costs and functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If chips are stacked over chips to form three-dimensional devices, then integration density and bandwidth are improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent segments the three-dimensional device into multiple functional layers: base die, intermediate dies with redistribution layers, and top dies. Each layer performs specific functions and can be manufactured independently, then assembled through controlled flip-chip bonding processes. This segmentation allows complex 3D integration to be broken down into manageable manufacturing steps.
Solution Approach 2:
The patent transitions from traditional planar (2D) chip arrangements to three-dimensional stacked configurations. By stacking chips vertically and using through-silicon vias for interconnection, the design exploits the third dimension to achieve higher integration density without proportionally increasing manufacturing complexity.
2Quantity of substance
If minimum feature size is reduced to increase integration density, then more components fit in given area, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the interconnection architecture from planar to vertical, using through-silicon vias that extend through the entire chip thickness. This parameter change allows signal routing in the vertical dimension, effectively increasing integration density without requiring proportional reduction in lateral feature sizes, thus maintaining manufacturability.
3Speed
If interconnect length is decreased to increase bandwidth, then data transfer speed improves, but device complexity increases
Solution Approach 1:
The patent moves interconnections from the lateral plane to the vertical dimension through through-silicon via structures. This dimensional transition dramatically shortens interconnect lengths between stacked chips, enabling higher bandwidth data transfer while the modular layering approach keeps the overall system complexity manageable.
4Reliability
If more through-silicon via structures are implemented to enhance device-to-device connections, then interconnectivity improves, but manufacturing cost and complexity increase
Solution Approach 1:
The patent implements preliminary actions by forming redistribution layers and via structures on individual dies before stacking. This allows interconnection structures to be prepared in advance on separate wafers, enabling parallel processing and reducing the complexity of real-time assembly operations.
Solution Approach 2:
The patent introduces intermediate redistribution layer dies that act as mediators between base and top dies. These intermediate layers provide additional routing opportunities and signal redistribution, enhancing overall interconnectivity while distributing the manufacturing complexity across multiple simpler stages rather than requiring direct complex connections between all components.
Data Source
AI summary
A die stack includes: a first die including a first semiconductor substrate; a first redistribution layer (RDL) structure disposed on a front surface of the first die and electrically connected to the first semiconductor substrate; a second die bonded to the front surface of the first die and including a second semiconductor substrate; a third die bonded to the front surface of the first die and including a third semiconductor substrate; a second RDL structure disposed on front surfaces of the second and third dies and electrically connected to the second and third semiconductor substrates; and a through dielectric via (TDV) structure extending between the second and third dies and electrically connected to the first RDL structure and second RDL structure. The second and third dies are disposed in a plane that extends perpendicular to a vertical stacking direction of the die stack.