3DIC Thermal Feature Stack With Graphene Heat Dissipation
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Solution Overview
Problem
Three-dimensional integrated circuits (3DICs) face performance and reliability issues due to inadequate heat dissipation, particularly at high temperatures, limiting their integration density and efficiency.
Innovation Solution
Incorporating thermal conductive layers with high thermal conductivity, such as 2D materials like graphene, within the semiconductor device structure to enhance heat dissipation between and beneath integrated components, while maintaining electrical isolation to prevent interference with device operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional integrated circuits (3DICs) are formed by bonding two or more chips or substrates together, then integration density is improved, but heat dissipation performance deteriorates leading to reliability issues at high temperature
Solution Approach 1:
The patent introduces thermal interface materials as intermediary substances between stacked semiconductor substrates to facilitate heat transfer. These materials serve as mediators that bridge the thermal gap between chips, enabling effective heat dissipation from upper substrates to lower substrates and ultimately to the heat sink, thereby resolving the heat accumulation problem in 3DIC structures
Solution Approach 2:
The patent replaces conventional mechanical bonding methods with direct thermal bonding or eutectic bonding techniques that simultaneously achieve both mechanical attachment and thermal conduction. This substitution eliminates the need for separate bonding and thermal management steps, as the bonding process itself creates thermally conductive joints that improve heat dissipation while maintaining structural integrity
2Quantity of substance
If more devices are integrated into one chip or die, then integration density is improved, but design complexity increases
Solution Approach 1:
The patent divides the integrated circuit system into multiple separate semiconductor substrates that are stacked vertically. Each substrate can be designed, fabricated, and tested independently with fewer devices per substrate, reducing the complexity of individual design processes while achieving high overall integration density through the three-dimensional stacking architecture
Solution Approach 2:
The patent transitions from two-dimensional planar integration to three-dimensional vertical integration by stacking multiple substrates in the thickness direction. This dimensional change allows devices to be distributed across multiple layers and substrates, reducing the complexity of routing and interconnections on any single substrate while maintaining high overall device density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively improves heat dissipation in 3DICs, reducing device failure and enabling higher integration densities by leveraging the superior thermal conductivity of materials like graphene, which is not electrically connected to power or signal sources.
Implementation Method 1
Incorporating thermal conductive layers with high thermal conductivity, such as 2D materials like graphene, within the semiconductor device structure to enhance heat dissipation
Data Source
AI summary
A semiconductor device package, along with methods of forming such, are described. The semiconductor device package includes a first semiconductor device structure having a first substrate, two first devices disposed on the first substrate, a first interconnection structure disposed over the first substrate and the two first devices, and a first thermal feature disposed through the first substrate and the first interconnection structure. The semiconductor device package further includes a second semiconductor device structure disposed over the first semiconductor device structure having a second interconnection structure disposed over the first interconnection structure, a second substrate disposed over the second interconnection structure, two second devices disposed between the second substrate and the second interconnection structure, and a second thermal feature disposed through the second substrate and the second interconnection structure. The second thermal feature is in contact with the first thermal feature.