3DIC Stack Through-Via Layout for Lower IR Drop
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Solution Overview
Problem
In three-dimensional integrated circuit (3DIC) stacks, the difference in distance between upper-level dies and external components leads to voltage drop issues, such as IR drop, due to increased resistance.
Innovation Solution
The implementation of through-vias that extend from the front side of the die to the interconnect structure on the back side, reducing resistance and mitigating voltage drop issues. Additionally, hybrid bonding processes with metal-to-metal and dielectric-to-dielectric bonding are used to enhance bonding strength, and testing structures are included for verification testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional two-dimensional integrated circuits are used, then manufacturing process is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from traditional two-dimensional integrated circuit layout to three-dimensional stacking architecture. Multiple semiconductor dies are vertically stacked and bonded together, utilizing the vertical dimension to achieve higher integration density. This dimensional change allows more functional components to be packed into a smaller footprint area while maintaining manufacturability through established bonding processes
2Productivity
If upper-level dies are placed farther from external components, then vertical integration is achieved, but voltage drop increases due to increased resistance
Solution Approach 1:
The patent introduces intermediate redistribution layers (RDLs) and bonding interfaces as mediators between upper-level dies and external components. These intermediate structures provide additional conductive pathways and signal routing options, effectively reducing the electrical distance and resistance between distant components. The hybrid bonding approach with embedded conductive vias creates low-resistance interconnections that mitigate voltage drop issues
3Strength
If hybrid bonding with metal-to-metal and dielectric-to-dielectric bonding is used, then bonding strength is enhanced, but manufacturing process complexity increases
Solution Approach 1:
The patent combines metal-to-metal bonding and dielectric-to-dielectric bonding into a single hybrid bonding process. Conductive metal pads on one die are simultaneously bonded to corresponding metal pads and dielectric regions on another die in one bonding step. This merged approach achieves superior bonding strength through multiple bonding mechanisms while streamlining the manufacturing process by eliminating separate bonding steps
Data Source
AI summary
A three-dimensional integrated circuit stack comprises a first integrated circuit structure, a second integrated circuit structure bonding to the first integrated circuit structure, and a redistribution structure. The first integrated circuit structure comprises a first semiconductor device, a first buffer structure, a first interconnect structure, a first conductive via, and a first through via. The first semiconductor device is located between the first buffer structure and the first interconnect structure. The first conductive via is extending through the first buffer structure and in contact with the first semiconductor device. The first through via is extending from the first buffer structure to the first interconnect structure. The redistribution structure is disposed on the first buffer structure, electrically connected to the first semiconductor device through the first conductive via, and electrically connected to the first interconnect structure through the first through via.