3DIC Die Package With Trench Capacitors for Power Integrity
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Solution Overview
Problem
The miniaturization of electronic devices increases the challenge of manufacturing decoupling capacitors in interconnect structures and interposers that meet size constraints and power integrity requirements in 3DIC die packages, leading to higher power supply noise.
Innovation Solution
Integration of trench capacitors within IC dies, which provide higher capacitance density without increasing the number of capacitors in interconnect structures or interposers, achieved through hybrid bonding with passive dies containing trench capacitors, allowing for reduced die package size while enhancing power delivery and integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If decoupling capacitors are integrated in interconnect structures and interposers, then power integrity can be improved, but device size increases and manufacturing complexity increases
Solution Approach 1:
The patent merges the decoupling capacitor function directly into the IC die by integrating capacitor structures (such as MIM capacitors, trench capacitors, or stacked capacitors) within the same die substrate that contains the active circuitry. This integration eliminates the need for separate interconnect structures or interposers dedicated to housing decoupling capacitors, thereby reducing overall device size while maintaining power integrity benefits.
Solution Approach 2:
The patent employs three-dimensional capacitor architectures (such as stacked capacitors extending vertically through multiple layers, or trench capacitors utilizing vertical depth) to increase capacitance density without expanding the lateral footprint. This dimensional transition from planar to vertical integration allows high capacitance values to be achieved within a compact area, resolving the contradiction between power integrity and device size.
2Reliability
If decoupling capacitors are integrated in interconnect structures and interposers, then power integrity can be improved, but manufacturing complexity increases
Solution Approach 1:
By merging capacitor fabrication steps with the existing IC manufacturing process flow, the patent eliminates the need for separate assembly steps for integrating decoupling capacitors. Capacitor structures are formed using standard semiconductor fabrication techniques (deposition, etching, doping) that are already part of the IC manufacturing process, thereby avoiding additional manufacturing complexity while achieving power integrity improvement.
Solution Approach 2:
The patent utilizes standard semiconductor materials and process parameters (such as metal layers, dielectric materials, and doping concentrations) that are already optimized in existing IC fabrication facilities. By designing capacitor structures that conform to existing process capabilities rather than requiring new process equipment or materials, the patent maintains manufacturing simplicity while achieving the desired power integrity enhancement.
3Area of stationary object
If device miniaturization is pursued, then device size decreases, but capacitance density requirements become harder to meet
Solution Approach 1:
The patent transitions from two-dimensional planar capacitor layouts to three-dimensional capacitor structures that utilize vertical space. Examples include stacked capacitors extending through multiple metal layers and trench capacitors utilizing the vertical depth of the substrate. This dimensional change enables capacitance density to increase proportionally with the number of stacked layers or trench depth, allowing high capacitance values to be achieved in miniaturized devices.
Solution Approach 2:
The patent implements nested capacitor structures where capacitor elements are embedded within or between other device components. For example, MIM capacitors are formed by nesting conductive plates within dielectric layers that are already part of the interconnect structure, or trench capacitors are formed by nesting conductive regions within etched trenches of the substrate. This nesting approach maximizes capacitance within the available three-dimensional space without increasing device footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The integration of trench capacitors in IC dies increases capacitance density, reducing power supply noise and maintaining compact die package size, thus addressing the power integrity challenges in 3DIC die packages.
Implementation Method 1
The capacitor includes a first conductive plate, a second conductive plate, and a dielectric layer between the first conductive plate and the second conductive plate
Implementation Method 2
a dielectric layer between the first conductive plate and the second conductive plate
Data Source
Figure 1A
Figure 1B
Figure 2A
AI summary
Various embodiments of a 3DIC die package, including trench capacitors integrated with IC dies, are disclosed. A 3DIC die package includes a first IC die and a second IC die disposed on the first IC die. The first IC die includes a substrate having a first surface and a second surface opposite to the first surface, a first active device disposed on the first surface of the substrate, and a passive device disposed on the second surface of the substrate. The passive device includes a plurality of trenches disposed in the substrate and through the second surface of the substrate, first and second conductive layers disposed in the plurality of trenches and on the second surface of the substrate, and a first dielectric layer disposed between the first and second conductive layers. The second IC die includes a second active device.