3DIC Logic Die TSV Layout for Faster Low-Loss Power Delivery
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Three-dimensional integrated circuits (3DICs) face challenges related to power transmission efficiency and speed due to the length of interconnects between stacked dies, leading to increased power loss and reduced performance.
Innovation Solution
The implementation of a die structure with at least one upper through-silicon via (TSV) and at least one lower TSV, allowing for power transmission to devices on opposite sides of the die structure, thereby reducing power loss and improving transmission speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor dies are stacked using package-on-package and system-in-package packaging techniques, then integration density is improved, but interconnect length between stacked dies increases causing power loss
Solution Approach 1:
The patent implements through-silicon vias (TSVs) that extend vertically through the substrate thickness, enabling direct electrical connection between stacked dies in the vertical dimension. This dimensional approach to interconnection reduces the effective current path length compared to lateral routing, thereby reducing power loss while maintaining high integration density through vertical stacking
2Ease of manufacture
If conventional packaging techniques are used, then manufacturing is simpler, but transmission speed between stacked dies is reduced
Solution Approach 1:
The patent segments the interconnection path into multiple vertical TSV stages, with each die stack forming a discrete module. This segmentation allows for standardized manufacturing processes for each module while achieving high transmission speeds through the vertical stacking architecture, as signals can be transmitted directly between adjacent dies without long lateral interconnects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables faster and more efficient power transmission across the die structure, reducing power loss and enhancing overall performance by utilizing wider conductive vias with lower resistance.
Implementation Method 1
The upper portion of the first logic die comprises a device layer and a power transmission layer, and the upper TSV penetrates through the device layer and physically connected to the power transmission layer
Data Source
AI summary
A package structure includes an interconnect structure, a first logic die, a molding material, a conductive via, and a redistribution layer. The interconnect structure is attached to a package substrate. The first logic die is disposed over the interconnect structure. The first logic die includes an upper through-silicon via (TSV) on the upper portion of the first logic die and a lower TSV on the lower portion of the first logic die. The upper portion of the first logic die includes a device layer and a power transmission layer, and the upper TSV penetrates through the device layer and physically connected to the power transmission layer. The molding material is over the interconnect structure and surrounds the first logic die. The conductive via penetrates through the molding material. The redistribution layer is over the first logic die and the molding material.