3DIC Via-Through-Substrate Interconnect for Flexible Die Stacking
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Solution Overview
Problem
The semiconductor industry faces challenges in integrating semiconductor devices with varying process nodes and functionalities efficiently and cost-effectively, particularly in three-dimensional integrated circuits (3DICs), where vertical stacking and flexible placement of devices are hindered by conventional interconnect methods.
Innovation Solution
The implementation of vias extending from the topmost conductive line of the interconnect structure to the backside of the semiconductor device, combined with aluminum interconnects in upper portions and copper in lower portions, allows for a unified design methodology in 3DICs, enabling integration of devices with different process nodes and functionalities, and facilitating vertical electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional interconnect methods are used in 3DICs, then manufacturing process is simpler, but vertical stacking and flexible placement of devices are hindered
Solution Approach 1:
The patent extends vias from the topmost conductive line through the substrate to the backside, adding a vertical dimension to the interconnect structure. This enables three-dimensional routing paths that allow devices to be stacked vertically and placed flexibly, transforming the traditional planar interconnect approach into a 3D architecture that supports advanced packaging configurations
Solution Approach 2:
The interconnect structure is segmented into multiple materials: aluminum for upper portions and copper for lower portions. This segmentation allows each material to be optimized for its specific function - aluminum for upper interconnects and copper for lower interconnects - while enabling complex 3D routing paths that support vertical stacking and flexible device placement
2Adaptability or versatility
If unified design methodology is implemented for 3DICs, then integration of devices with different process nodes is enabled, but production cost increases
Solution Approach 1:
The patent changes material parameters by using aluminum for upper portions and copper for lower portions of the interconnect structure. This parameter change enables unified design methodology that can integrate devices from different process nodes, as the multi-material approach provides design flexibility while the standardized via extension process maintains manufacturing efficiency and controls costs
3Ease of operation
If via extension method is used, then electrical routing flexibility is improved, but manufacturing complexity increases
Solution Approach 1:
The via extension structure serves multiple functions: it provides vertical electrical connection from top to backside, enables flexible routing paths for different device configurations, and supports integration of devices with different process nodes. This multi-functional design achieves routing flexibility while maintaining a standardized structure that does not significantly increase manufacturing complexity
Data Source
AI summary
A package includes a die. The die includes: a substrate; electrical components at a front side of the substrate; an interconnect structure at the front side of the substrate and electrically coupled to the electrical components, where an uppermost conductive line of the interconnect structure is an aluminum line; and a via extending from the uppermost conductive line to a backside of the substrate. The package further includes: a molding material around the die; a first redistribution structure (RDS) under the die and the molding material; a second RDS over the die and the molding material, where each of the first RDS and the second RDS comprises dielectric layers and conductive features in the dielectric layers, where the via of the die is electrically coupled to the first RDS and the second RDS; and a second die over and electrically coupled to the second RDS.