Multi-Step Wafer Stack Trimming for 3DIC Edge Strength

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Solution Overview

Problem

The thinning of semiconductor wafers during the fabrication of 3DICs leads to sharp edges with low mechanical strength, causing chipping and flaking due to stress and debris accumulation during edge trimming processes, which can damage the wafer stack.

Innovation Solution

A multi-step edge trimming process is employed, involving different types of edge trimming cuts to minimize stress and damage, including bonding a second wafer to a first wafer and performing sequential edge trimming cuts using up-cuts and down-cuts to reduce shear stress and pressure on the wafer stack.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If wafer thinning is performed during 3DIC fabrication, then device density and integration are improved, but edge mechanical strength deteriorates causing chipping and flaking

Engineering Contradiction:
Improvewafer thicknessVSAvoidedge mechanical strength
Core Design Contradiction:
Volume of moving objectVSStrength

Solution Approach 1:

The edge trimming process is divided into multiple sequential cuts (first edge trimming cut, second edge trimming cut, third edge trimming cut) rather than a single deep cut. Each cut removes a portion of the peripheral material progressively, reducing stress concentration and preventing chipping while achieving the desired edge geometry on thinned wafers.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Edge trimming operations are performed at specific stages during the wafer stacking and bonding process. The first edge trimming cut is performed on the second wafer before bonding, and subsequent trimming cuts are performed on the stacked wafer assembly, preparing the edges in advance to prevent damage during subsequent processing steps.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If edge trimming is performed on thinned wafers, then peripheral material is removed to improve integration, but stress accumulation increases causing damage

Engineering Contradiction:
Improveedge geometry precisionVSAvoidstress accumulation
Core Design Contradiction:
Manufacturing precisionVSStress or pressure

Solution Approach 1:

The trimming process is segmented into multiple shallow cuts rather than one deep cut. Each cut removes a small portion of material, distributing the stress removal process over multiple steps and preventing excessive stress accumulation that would occur with a single aggressive trimming operation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Edge trimming is performed periodically at different stages of the fabrication process (before bonding, after bonding, and at intermediate stages). This periodic intervention allows stress to be managed in controlled increments rather than allowing continuous stress accumulation during a single prolonged trimming operation.

Inventive Principle:
Principle #19Periodic action

3Productivity

If debris accumulates during edge trimming, then trimming effectiveness is improved, but wafer damage increases due to debris-induced stress

Engineering Contradiction:
Improvetrimming efficiencyVSAvoiddebris-induced damage
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

Edge trimming is performed at multiple stages during the wafer stacking process, removing debris-prone peripheral material before it can cause damage. The first edge trimming cut removes material from the second wafer before bonding, and subsequent cuts remove material from the stacked assembly, preventing debris accumulation that would occur during later processing steps.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The multi-step edge trimming process effectively reduces damage to the multi-dimensional integrated chip structure by mitigating stress and preventing chipping and flaking, ensuring the integrity of the wafer stack.

Implementation Method 1

bonding a second wafer to a first wafer

Methodology Applied
Scientific EffectAdhesion: Adhesive

Data Source

PatentUS20250241053A1Techniques for wafer stack processing
Publication Date: 2025.07.24 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250241053A1 patent drawing
  • US20250241053A1 patent drawing
  • US20250241053A1 patent drawing

AI summary

The present disclosure, in some embodiments, relates to method. The method includes bonding a second wafer to a first wafer to form a multi-dimensional integrated chip structure. A first edge trimming cut is performed at a first lateral distance from a central region of the multi-dimensional integrated chip structure. A second edge trimming cut is performed at a second lateral distance from the central region of the multi-dimensional integrated chip structure. The second lateral distance is larger than the first lateral distance.