3DS DRAM Stack Interface Gating for Lower Active Power
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Solution Overview
Problem
Conventional three-dimensional (3DS) DRAM stacks suffer from high power consumption due to active signaling resources in all dies during memory access transactions, exceeding the ideal active-idle power consumption.
Innovation Solution
Implementing a load-reduced 3DS DRAM architecture that selectively enables/disables physical signaling interfaces in non-targeted dies based on pre-transmitted chip identifier information, reducing power consumption by disabling unnecessary signal reception and processing in non-targeted dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all dies in a 3DS DRAM stack maintain active signaling resources during memory access transactions, then all dies can respond to commands, but power consumption exceeds the ideal active-idle level
Solution Approach 1:
The patent applies preliminary action by transmitting the chip identifier (CID) before the command signal, allowing non-targeted dies to proactively disable their signaling resources before the command arrives. This early identification and selective disabling reduces power consumption while ensuring the targeted die remains ready to execute the command.
Solution Approach 2:
The patent implements local quality by enabling different operational states for different dies within the same 3DS stack. Non-targeted dies transition to a low-power disabled state while the targeted die maintains active signaling resources, allowing each die to have optimized power characteristics based on its specific role in the current transaction.
2Use of energy by moving object
If signaling resources are disabled in non-targeted dies, then power consumption approaches ideal levels, but command execution timing must be coordinated
Solution Approach 1:
The CID is transmitted in advance of the command signal, providing a time window for non-targeted dies to disable their signaling resources before the command arrives. This preliminary identification eliminates timing conflicts because the disable decision is made before the command execution window begins.
Solution Approach 2:
The chip identifier (CID) acts as an intermediary signal that mediates between the memory controller and the individual dies. By using the CID as an intermediate step before command execution, the system can coordinate resource disabling without directly interfering with the command timing, thus avoiding execution delays.
3Use of energy by moving object
If chip identifier transmission is separated from command transmission, then selective disabling can occur, but additional signaling resources are required
Solution Approach 1:
The patent achieves universality by transmitting the chip identifier through existing command/address signaling pathways that are already present in conventional 3DS DRAM architectures. This multi-functional use of existing infrastructure avoids adding dedicated CID signaling lines, thereby reducing the increase in device complexity while still enabling selective power management.
Data Source
AI summary
Power consumption in a three-dimensional stack of integrated-circuit memory dies is reduced through selective enabling/disabling of physical signaling interfaces in those dies in response to early transmission of chip identifier information relative to command execution.