3DS Memory Master Die Selection for Timing Margin Recovery
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Solution Overview
Problem
Conventional memory devices with three-dimensional stacks (3DS) face issues due to varying process corners of memory dies, leading to unrecoverable failures and inefficient debug operations, as well as reduced yield and increased costs due to inadequate timing margins and unrecoverable failures on the master memory die.
Innovation Solution
Implementing master die selection circuitry that allows for post-packaging selection of memory dies with preferable design margins, enabling any die in the 3DS to receive command and address signals, and allowing for dynamic switching of master and slave roles to maintain functionality even in the event of unrecoverable failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory devices are built with fixed master die assignment during packaging, then manufacturing process is simple, but timing margins are inadequate and failures are unrecoverable
Solution Approach 1:
The patent implements dynamic master die selection capability where any memory die in the 3DS can be designated as master through selection circuitry. This allows the system to adaptively choose the most suitable die as master based on process corner characteristics, and to switch masters if failures occur, transforming the static master assignment into a dynamic, reconfigurable role assignment.
Solution Approach 2:
The patent changes the operational parameter of master die selection from fixed to variable. By implementing selection circuitry that can identify and designate different dies as master based on their process corner characteristics (fast/slow, high/low voltage), the system optimizes timing margins by matching master slave pairs with compatible electrical characteristics.
2Productivity
If memory dies with varying process corners are stacked, then manufacturing yield is reduced, but fabrication costs and debug time increase
Solution Approach 1:
The patent performs preliminary characterization of each memory die's process corner characteristics (fast/slow, high/low voltage) during manufacturing. This pre-screening information is stored and used by the selection circuitry to automatically identify suitable master slave pairs, eliminating the need for time-consuming post-packaging debug operations and enabling higher manufacturing yield by recovering dies that would otherwise be discarded.
3Manufacturing precision
If master die is fixed at bottom position in 3DS, then device structure is simple, but timing margins are inadequate due to process corner variations
Solution Approach 1:
The patent applies local quality by allowing different memory dies to have different functional roles (master or slave) based on their individual process corner characteristics. Instead of uniformly assigning master role to the bottom die, the system evaluates each die's electrical characteristics and assigns roles locally optimized for timing margin performance.
Data Source
AI summary
Memory devices and systems with post-packaging master die selection, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory dies. Each memory die of the plurality includes a command/address decoder. The command/address decoders are configured to receive command and address signals from external contacts of the memory device. The command/address decoders are also configured, when enabled, to decode the command and address signals and transmit the decoded command and address signals to every other memory die of the plurality. Each memory die further includes circuitry configured to enable, or disable, or both individual command/address decoders of the plurality of memory dies. In some embodiments, the circuitry can enable a command/address decoder of a memory die of the plurality after the plurality of memory dies are packaged into a memory device.