3DSFET Standard Cell Architecture With PN Junction Isolation
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Solution Overview
Problem
The manufacturing of 3D stacked field-effect transistor (3DSFET) devices faces challenges due to high device density requirements, including high-aspect ratio patterning and isolation issues, which lead to contact resistance problems and short-circuit risks, especially in forming different channel-width transistors with complex processes and dielectric layer etching.
Innovation Solution
The implementation of a PN junction structure that electrically isolates lower and upper source/drain regions, allowing for reverse-biased operation to prevent current flow and simplify the connection between source/drain regions, thereby eliminating the need for additional contact plugs and dielectric layers, enhancing device density and manufacturing simplicity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If different channel-width transistors are used to address connection issues, then the middle-of-line structure can be connected outside the 3DSFET, but the overall footprint increases and manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar isolation methods to vertical 3D isolation by forming the dielectric layer between vertically stacked source/drain regions. This dimensional change allows isolation without increasing lateral footprint, as the separation occurs in the vertical dimension between stacked transistors rather than in the lateral plane.
Solution Approach 2:
The dielectric layer is nested within the vertical stack structure, positioned between the lower and upper source/drain regions. This nesting approach integrates the isolation function into the existing 3D stack architecture without requiring additional lateral space or separate isolation structures.
2Ease of manufacture
If different channel-width transistors are used, then connection outside the 3DSFET is possible, but manufacturing process becomes complicated
Solution Approach 1:
The patent merges the isolation function with the source/drain region formation process. The dielectric layer is formed as part of the source/drain structure fabrication, combining what would traditionally be separate isolation and connection steps into a unified process flow that reduces overall manufacturing complexity.
Solution Approach 2:
The dielectric layer serves multiple functions simultaneously: it provides electrical isolation between stacked source/drain regions, enables vertical stacking architecture, and facilitates connection structures. This multi-functionality reduces the need for separate dedicated isolation structures and simplifies the overall manufacturing process.
3Ease of manufacture
If dielectric layer etching is performed to provide space for upper source/drain region, then upper epitaxial structure can be grown, but manufacturing complexity increases and short-circuit risk remains
Solution Approach 1:
The dielectric layer is formed between source/drain regions before the upper epitaxial structure growth step. This preliminary formation of the dielectric layer ensures that the isolation structure is in place before subsequent processing, eliminating the need for complex etching operations to create space and reducing short-circuit risks by establishing isolation early in the process flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The PN junction structure effectively isolates source/drain regions, reducing manufacturing complexities and improving device performance and density by eliminating the need for additional contact plugs and dielectric layers, while maintaining efficient signal transfer and isolation.
Implementation Method 1
a PN junction structure formed between a lower source/drain region and an upper source/drain region... the PN junction structure is formed to electrical isolate the lower source/drain region and the upper source/drain region
Data Source
Figure 1
Figure 2A~2B
Figure 3A~3B
AI summary
Provided is a three-dimensionally stacked field-effect transistor (3DSFET) device (500) which includes: a 1st lower source/drain region (512L) and a 2nd lower source/drain region (512R) connected to each other through a 1st lower channel structure (510) controlled by a 1st gate structure (515); and a 1st upper source/drain region (522L) and a 2nd upper source/drain region (522R), respectively above the 1st lower source/drain region and the 2nd lower source/drain region, and connected to each other through a 1st upper channel structure (520) controlled by the 1st gate structure (515), wherein the 2nd lower source/drain region and the 2nd upper source/drain region form a PN junction therebetween.