3-Level Memory Cell Page Buffer for Nonvolatile Semiconductor Reliability
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Solution Overview
Problem
4-level non-volatile semiconductor memory devices face reliability issues due to narrow threshold voltage margins, leading to incorrect data reading caused by electron leakage, which reduces their storage capacity and integration density.
Innovation Solution
A non-volatile semiconductor memory device with 3-level memory cells and a page buffer system that maps bit data to threshold voltage levels, using a row decoder and page buffer to control word lines and bit lines, enhancing data storage states and reliability by increasing the interval between threshold voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 4-level memory cells are used to increase data storage capacity, then integration density is improved, but reliability deteriorates due to narrow threshold voltage margins
Solution Approach 1:
The patent changes the threshold voltage levels from 4 distinct levels to 3 distinct levels (first, second, and third threshold voltage groups). This parameter change increases the margin between neighboring threshold voltages, preventing electron leakage-induced threshold voltage crossings while maintaining enhanced integration density compared to 2-level cells.
2Quantity of substance
If 4-level memory cells are used to double data storage capacity, then integration density is improved, but device complexity increases due to narrow voltage margins
Solution Approach 1:
The patent simplifies the threshold voltage structure by reducing from 4 levels to 3 levels, which decreases the control complexity required for programming and reading operations while maintaining higher integration density than 2-level cells.
3Quantity of substance
If 3-level memory cells are used to increase integration density, then data storage capacity is improved, but threshold voltage margin is reduced
Solution Approach 1:
The patent optimizes the threshold voltage groups (first, second, and third groups with different voltage levels) to achieve an optimal balance between integration density and threshold voltage margin, preventing electron leakage from causing incorrect threshold voltage readings.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 3-level memory cell design improves data storage capacity and integration density while increasing reliability by expanding the threshold voltage intervals, outperforming both 2-level and 4-level devices in terms of integration and reliability.
Implementation Method 1
the floating gate FG traps electrons. These trapped electrons establish a threshold voltage of the memory cell MC
Data Source
AI summary
A non-volatile semiconductor memory device includes a memory array having nonvolatile memory cells. The memory device also includes a page buffer coupled to the memory array through first and second common bit lines and configured to map a set of first to third bit data to threshold voltage levels of a pair of first and second memory cells. The memory device also includes a row decoder configured to control a word line of a selected memory cell of the memory array. The page buffer includes a switch, a first latch block, a second latch block, a dumping block, and an output block.