3N-4-Level Voltage Inverter Topology for Harmonic Reduction
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Solution Overview
Problem
Existing multi-level voltage inverters, such as three-level NPC-type inverters, generate significant voltage harmonics, requiring large sinus filters, and upgrading to higher levels like five-level inverters increases costs substantially due to the need for additional IGBT transistors and diodes.
Innovation Solution
A novel 3N−4-level voltage inverter topology with N−1 series-connected elementary generators and additional commutation branches with bidirectional switches and diodes, reducing voltage harmonics while minimizing additional costs by optimizing the power/cost ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If the number of voltage levels is increased from three-level to five-level NPC inverter, then voltage harmonics are reduced, but the number of IGBT transistors and diodes increases substantially, leading to higher costs
Solution Approach 1:
The inverter is divided into modular units: N-1 direct voltage generators are segmented into series-connected elementary generators (3N-5 total), and commutation branches are organized into first commutation branches (with commutation cells) and second commutation branches (with bidirectional switches). This segmentation allows achieving higher voltage levels (3N-4 levels) while maintaining manageable component distribution and reducing the simultaneous presence of expensive IGBT transistors and diodes.
Solution Approach 2:
Different parts of the inverter use different switching device configurations optimized for their specific functions: the first commutation branches use commutation cells with IGBT transistors and diodes for voltage clamping, while the second commutation branches use bidirectional switches for active commutation. This local optimization reduces the overall count of expensive components while maintaining the ability to generate multiple voltage levels and reduce harmonics.
2Object-generated harmful factors
If filter means are added to reduce output voltage harmonics, then variable-speed applications become feasible, but the inverter size and cost increase
Solution Approach 1:
The inverter topology itself performs preliminary harmonic reduction by generating a multi-level output voltage waveform (3N-4 levels) that inherently has lower harmonic content compared to conventional two-level inverters. This preliminary action reduces the burden on external filter means, allowing for smaller or even eliminated sinus filters in variable-speed applications.
Solution Approach 2:
The inverter changes the voltage output parameters by producing multiple discrete voltage levels (3N-4 levels) instead of a single bipolar level. This parameter change in the voltage waveform shape directly reduces voltage harmonics at the source, eliminating the need for large filter components and reducing the overall inverter volume.
3Device complexity
If conventional NPC inverter architecture is used, then the structure is simple and well-established, but voltage harmonics are rich and require large filter means
Solution Approach 1:
The conventional NPC inverter structure is extended through segmentation into multiple voltage levels (3N-4 levels) using N-1 series-connected direct voltage generators and multiple commutation branches. This segmentation maintains the structural clarity of NPC inverters while fundamentally improving the output voltage waveform quality and reducing harmonics without requiring large external filters.
Data Source
AI summary
The invention relates to a 3N−4-level (N≧3) voltage converter including:3N−5 direct voltage generators (1, 2, 3, 4) connected between two input voltage terminals (V+, V−),two lateral commutation branches (10, 11), each connected between an output terminal and an input voltage terminal (V+, V−) and comprising N−1 series connected commutation cells (20, 21, 22, 23),2N−4 central commutation branches (12, 13), each comprising a switch bidirectional in terms of voltage and current and being connected between two commutation cells of a lateral branch (10, 11) and two generators, andN−2 pairs of diode cells (16) each connected to two of the 2N−4 central commutation branches (12, 13). The diodes (14, 15) of one pair are series connected, in the same direction, and are connected together by a middle point connected between two generators.