3T Dynamic-Analog RAM Cell for Low-Power CIM CNN Accelerators
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Solution Overview
Problem
Existing computing-in-memory (CIM) technologies for accelerating convolutional neural network (CNN) operations are limited by the use of conventional 6-transistor or 8-transistor digital SRAM cells, which restrict the size of CIM arrays and incur higher transistor counts and power consumption.
Innovation Solution
A 3-transistor dynamic-analog RAM (DARAM) cell is introduced, which reduces transistor count and operation complexity, enabling 4-bit weight storage as an analog voltage and employing techniques like rectified linear unit (ReLU) based early termination, analog weight shifting, and leakage reduction to achieve state-of-the-art efficiency and area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional 6-transistor or 8-transistor digital SRAM cells are used for CIM, then reliability and stability are improved, but transistor count and area consumption increase
Solution Approach 1:
The patent extracts only the essential function of storing analog voltage representing weight values, removing unnecessary digital read/write circuitry and control logic from conventional SRAM cells. This extraction enables using simpler 3T memory cells that retain only the core charge-storage capability while discarding complex digital access mechanisms, thereby reducing area while maintaining functional reliability for analog computing operations.
Solution Approach 2:
The patent employs disposable-like simplified 3T memory cells that do not require the robustness and complexity of conventional 6T/8T SRAM cells. These simplified cells are optimized for single-use analog weight storage without needing to maintain data over long periods or withstand frequent digital read/write cycles, allowing area reduction while accepting reduced individual cell longevity in exchange for overall system efficiency.
2Measurement precision
If conventional 6-transistor or 8-transistor digital SRAM cells are used for CIM, then data retention and accuracy are improved, but power consumption increases
Solution Approach 1:
The patent extracts only the essential charge-storage function from conventional SRAM cells, removing power-hungry digital read/write circuitry, sense amplifiers, and control logic. The resulting 3T memory cell structure retains the core capability of storing analog voltage representing weight values while eliminating the majority of power consumption sources, achieving comparable accuracy with significantly reduced power usage.
Solution Approach 2:
The patent employs simplified memory cells optimized for analog weight storage without requiring the robust data retention and frequent refresh operations of digital SRAM. These cells accept reduced individual cell longevity but achieve superior power efficiency by eliminating complex digital access circuitry, maintaining sufficient accuracy for neural network operations.
3Area of stationary object
If 3T dynamic-analog RAM cells are used, then area efficiency and transistor count are improved, but device complexity and operation complexity increase
Solution Approach 1:
The patent merges the memory storage function with the computing function by using the same 3T memory cell structure for both weight storage and analog multiply-accumulate operations. This merging eliminates the need for separate digital read/write circuitry and control logic, reducing overall device complexity despite the novel operation mode. The memory cell directly participates in computing operations, simplifying the overall system architecture.
Solution Approach 2:
The patent makes the 3T memory cell multi-functional by enabling it to perform both weight storage and analog computing operations within the same structure. The cell operates in different modes (write, hold, read/compute) depending on the phase, eliminating the need for separate digital and analog circuitry. This universality reduces overall device complexity while maintaining area efficiency.
4Area of stationary object
If 3T dynamic-analog RAM cells are used, then area efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the operating parameters and mode of the 3T memory cell to accommodate manufacturing variations. By operating in analog mode with controlled voltage ranges and using differential readout techniques, the system becomes more tolerant of transistor parameter variations. The analog nature of operation allows for statistical compensation of manufacturing mismatches, reducing the stringency of precision requirements compared to digital operation.
Solution Approach 2:
The patent employs dynamic operation modes where the memory cell transitions between different states (write, hold, read/compute) with controlled timing and voltage levels. This dynamic operation allows the system to adapt to manufacturing variations by adjusting operation timing and voltage thresholds, reducing the impact of transistor matching precision limitations while maintaining area efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a significant reduction of transistor count, energy efficiency, and area efficiency, with an effective bit area smaller than traditional SRAM cells, and supports higher precision computations with minimal throughput degradation and negligible accuracy loss, achieving 8× system energy efficiency improvement and 3× area reduction compared to prior works.
Implementation Method 1
a memory node MEM in electrical communication between the read-access transistor M1 and the write-access transistor M3, wherein the memory node MEM is configured to store a 4-bit weight WE
Data Source
AI summary
Systems formed by a multi-bit three-transistor (3T) memory cell (i.e., dynamic-analog RAM) are provided. The 3T memory cell includes: a read-access transistor M1 in electrical communication with a read bitline; a switch transistor M2 in electrical communication with the read-access transistor M1; a write-access transistor M3 in electrical communication with the read-access transistor M1 and a write bitline; and a memory node MEM in electrical communication between the read-access transistor M1 and the write-access transistor M3, wherein the memory node MEM is configured to store a 4-bit weight WE. An array of the 3T memory cells (i.e., dynamic-analog RAMs) may form a computing-in-memory (CIM) macro, and further form a convolutional neural network (CNN) accelerator by communicating with an application-specific integrated circuit (ASIC) which communicates with a global weight static random access memory and an activation static random access memory.