3T DRAM Cell Supplemental Capacitance Retention
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Solution Overview
Problem
Three-transistor dynamic random access memory (3T DRAM) cells face challenges in retention time due to gate leakage currents, making them less attractive for scaled technology, while six-transistor static random access memory (6T SRAM) cells are less efficient in terms of size and performance, and one-transistor DRAM cells have higher process costs and lower performance.
Innovation Solution
Incorporating supplemental capacitance into the storage node of the 3T DRAM cell, either through additional metallization levels, increased parasitic capacitance, or metal-insulator-metal (MIM) capacitors, to extend the refresh interval and improve retention time without significant increases in process cost or cell area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If supplemental capacitance is added to the storage node, then retention time is improved, but device complexity increases
Solution Approach 1:
The supplemental capacitance is formed by nesting additional metallization layers (e.g., M3, M4, M5) within the existing memory cell structure. These nested conductive layers create capacitance through their overlapping geometry without requiring separate external capacitor components, thus improving retention time while minimizing added complexity.
Solution Approach 2:
Instead of adding capacitance through additional planar elements in the same layer, the invention utilizes the vertical dimension by stacking multiple metallization layers. This dimensional transition from 2D to 3D space allows capacitance to be generated within the existing cell footprint, avoiding area expansion while enhancing retention characteristics.
2Duration of action of stationary object
If additional metallization levels are used to increase capacitance, then retention time is improved, but manufacturing cost increases
Solution Approach 1:
The additional metallization layers serve multiple functions: they provide supplemental capacitance for retention, act as interconnect layers for signal routing, and can function as diffusion barriers or stress control layers. This multi-functionality eliminates the need for dedicated capacitor structures, reducing manufacturing complexity and cost while achieving improved retention time.
Solution Approach 2:
The invention merges the capacitance-forming function with the existing interconnect metallization layers. By combining storage functionality with interconnect functionality in the same structural elements, the design avoids separate processing steps for capacitor formation, thereby reducing manufacturing cost while achieving the desired retention time improvement.
3Duration of action of stationary object
If cell area is increased to accommodate larger capacitance structures, then retention time is improved, but integration density decreases
Solution Approach 1:
The invention transitions from planar capacitance structures to vertically-stacked metallization layers. By utilizing the third dimension (vertical stacking of M3, M4, M5 layers), sufficient capacitance is generated within the existing cell footprint, achieving improved retention time without increasing the lateral cell area and maintaining high integration density.
Solution Approach 2:
The capacitance-generating metallization layers are nested within the existing cell structure, utilizing the vertical space above and below the transistor channels. This nested arrangement creates the required capacitance volume without expanding the cell's lateral dimensions, thereby improving retention time while preserving integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The addition of supplemental capacitance increases the retention time of the 3T DRAM cell by 24% to 129% compared to baseline, providing a cost-effective solution that enhances performance and reduces the need for additional processing steps.
Implementation Method 1
a supplemental capacitance connected to the storage node and configured to extend a refresh interval of the 3T DRAM cell
Data Source
AI summary
A 3T DRAM cell includes a first transistor having a first control element connected as a storage node and a second transistor connected between the first transistor and a read bit line having a second control element connected to a read word line. The 3T DRAM cell also includes a third transistor connected between the storage node and a write bit line having a third control element connected to a write word line. Additionally, the DRAM cell includes a supplemental capacitance connected to the storage node and configured to extend a refresh interval of the 3T DRAM cell. A method of operating an integrated circuit having a 3T DRAM cell includes providing a memory state on a storage node of the 3T DRAM cell and extending a refresh interval of the memory state with a supplemental capacitance added to the storage node.