3T DRAM Cell Layout Using Gate Capacitance and Shared Bit Line
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Solution Overview
Problem
Existing dynamic random access memory cells require a three-dimensional capacitor configuration, increasing production costs and access time, and are not suitable for system-on-chip applications due to high leakage current and space requirements.
Innovation Solution
A three-transistor dynamic random access memory cell design with a shared bit line for read and write paths, utilizing a complementary field-effect-transistor architecture, which reduces cell area and integrates seamlessly with existing transistor processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a three-dimensional capacitor configuration is used in dynamic random access memory cells, then the memory can store data, but the production cost increases and access time increases
Solution Approach 1:
The patent extracts the capacitor component from the memory cell design, transitioning from a traditional 1T1C (one transistor, one capacitor) or 2T2C (two transistors, two capacitors) configuration to a 3T (three transistor) configuration. This removes the need for three-dimensional capacitor structures, thereby reducing production complexity and access time while maintaining data storage functionality through the gate capacitance of the third transistor.
Solution Approach 2:
The patent replaces the physical capacitor structure with an equivalent electrical function implemented through transistor gate capacitance. The third transistor's gate serves as the storage node, eliminating the need for separate capacitor components and their associated three-dimensional configurations, thus reducing both production cost and access time.
2Reliability
If traditional dynamic random access memory cells are used, then data can be stored, but leakage current is high and space requirements are large
Solution Approach 1:
The patent employs the third transistor (storage transistor) to actively manage and maintain the stored data state. The storage transistor's gate capacitance serves as the storage node, and the transistor itself participates in the refresh operation by being turned on during refresh cycles to maintain the stored charge, thereby reducing leakage current through active self-management rather than passive storage.
3Reliability
If traditional dynamic random access memory cells are used, then data can be stored, but space requirements are large
Solution Approach 1:
The patent merges the storage function with the transistor structure itself. The gate of the third transistor serves dual purposes: controlling the transistor's operation and simultaneously serving as the storage node for data. This integration eliminates the need for separate capacitor components and reduces the overall cell area compared to traditional designs that require dedicated capacitor structures.
Solution Approach 2:
The third transistor serves multiple functions: it acts as a switch for data access, provides gate capacitance for data storage, and participates in the refresh operation. This multi-functionality reduces the need for additional dedicated components, thereby minimizing the overall cell area while maintaining data storage capability.
Data Source
AI summary
Memory devices and related methods are disclosed. A memory cell can include one or more first conduction channels extending along a first lateral direction, overlaid by a first gate structure and a parallel second gate structure, both extending along a second lateral direction. A second conduction channel can be disposed parallel to the first conduction channels. A third gate structure can overlay the second conduction channel. The device can further include a first interconnect structure extending along the second lateral direction, overlying both the first and second conduction channels, and a second interconnect structure extending along the second lateral direction and overlying only the first conduction channels.