3T DRAM In-Memory Logic With Non-Destructive Data Inversion
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Solution Overview
Problem
Conventional DRAM memory cells require additional latches for data inversion during logical operations, leading to increased power consumption and read-to-read delays due to destructive read operations.
Innovation Solution
Implementing 3T DRAM memory cells that can invert data without additional latches, allowing logical operations to be performed directly within the memory cells, reducing the need for external processing resources and minimizing data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional DRAM memory cells are used for logical operations, then data inversion requires additional latches, but this increases device complexity and power consumption
Solution Approach 1:
The patent merges the data inversion function with the memory cell structure itself by utilizing the inherent charge storage and transfer capabilities of the 3T DRAM cell. The intermediate node between transistors serves dual purposes: storing data and enabling inversion operations, eliminating the need for separate latch structures.
Solution Approach 2:
The memory cell performs its own inversion operation through controlled charge transfer between its internal nodes. By applying appropriate voltages to the transistors, the cell inverts its stored data state without requiring external latch circuits, making the inversion capability self-contained within the memory cell structure.
2Ease of operation
If additional latches are used for data inversion, then logical operations can be performed, but read-to-read delays increase
Solution Approach 1:
The patent prepares the memory cell for inversion operations by maintaining charge in the intermediate node during standby states. This preliminary charging allows the inversion to occur rapidly when needed, avoiding the delays associated with charging capacitors through resistive paths during active operations.
3Productivity
If destructive read operations are used, then data can be read from memory cells, but multiple word lines cannot be fired without refreshing data
Solution Approach 1:
The patent enables continuous non-destructive read operations by maintaining charge on the intermediate node through controlled transistor gating. The memory cell retains its data state during read operations, allowing multiple sequential reads and word line activations without requiring periodic refresh cycles, thus maintaining continuous productive operation.
Data Source
AI summary
The present disclosure includes apparatuses and methods related to logical operations using memory cells. An example apparatus comprises a first memory cell controlled to invert a data value stored therein and a second memory cell controlled to invert a data value stored therein. The apparatus may further include a controller coupled to the first memory cell and the second memory cell. The controller may be configured to cause performance of a logical operation between the data value stored in the first memory cell and the data value stored in the second memory cell.