3T DRAM Memory Cells for In-Memory Logic Without Inversion Latches
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Solution Overview
Problem
Conventional DRAM memory cells require additional latches for data inversion during logical operations, leading to increased power consumption and read-to-read delays due to destructive read operations.
Innovation Solution
Implementing 3T DRAM memory cells that can invert data without additional latches, allowing logical operations to be performed directly within the memory cells, reducing the need for external processing resources and minimizing data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional DRAM memory cells are used for logical operations, then data inversion can be performed, but additional latches are required which increases device complexity and power consumption
Solution Approach 1:
The patent merges the data inversion function with the existing memory cell structure by utilizing the natural charge discharge behavior of the capacitor and the state changes of the transistors during read operations. This eliminates the need for separate inversion latches, reducing device complexity while maintaining inversion capability.
Solution Approach 2:
The memory cell performs data inversion automatically through its inherent operational characteristics. When a read operation is performed, the capacitor discharges and transistor states change, naturally inverting the data without requiring external inversion circuitry or additional power-consuming latch components.
2Speed
If conventional DRAM memory cells perform read operations, then data can be accessed, but destructive read operations occur requiring refresh cycles which increase read-to-read delays
Solution Approach 1:
The patent performs data inversion as a preliminary action during the read operation itself, rather than as a separate subsequent step. By inverting data during the read process, the system eliminates the need for additional refresh cycles to restore data, reducing read-to-read delays while maintaining fast access speeds.
3Adaptability or versatility
If additional latches are used for data inversion, then logical operations can be performed, but power consumption increases
Solution Approach 1:
The memory cell performs data inversion automatically through its inherent operational characteristics. When a read operation is performed, the capacitor discharges and transistor states change, naturally inverting the data without requiring external inversion circuitry or additional power-consuming latch components.
4Productivity
If data is accessed via bus between external processing resources and memory array, then processing can be performed, but processing time increases
Solution Approach 1:
The patent merges the processing resource with the memory array by implementing logical operation capabilities directly within the memory cell structure. This integration eliminates the need for data to be transferred via bus to external processing resources, significantly reducing processing time while maintaining full processing capability.
Data Source
AI summary
The present disclosure includes apparatuses and methods related to logical operations using memory cells. An example apparatus comprises a first memory cell controlled to invert a data value stored therein and a second memory cell controlled to invert a data value stored therein. The apparatus may further include a controller coupled to the first memory cell and the second memory cell. The controller may be configured to cause performance of a logical operation between the data value stored in the first memory cell and the data value stored in the second memory cell.