3T DRAM Cell Architecture Without 3D Capacitors
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Solution Overview
Problem
Dynamic random access memory cells face challenges in reducing area usage and process complexity due to the need for three-dimensional capacitors and destructive read/write operations, which hinder their integration in system-on-chip applications.
Innovation Solution
A three-transistor dynamic random access memory cell architecture that eliminates the need for a three-dimensional capacitor, using a write transistor, read transistor, and storage transistor with shared bit lines and a complementary field-effect transistor configuration to reduce area and maintain non-destructive read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional capacitors are used in dynamic random access memory cells, then storage capacity is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent extracts and eliminates the three-dimensional capacitor component from the memory cell architecture. By using a different mechanism (floating diffusion region with read transistor) to store and retrieve data, the complex 3D capacitor structure is removed entirely, simplifying the device while maintaining storage functionality
Solution Approach 2:
The patent replaces the complex, expensive three-dimensional capacitor with a simpler, easier-to-manufacture floating diffusion region. This substitution uses standard semiconductor fabrication processes without requiring complex 3D stacking, thereby reducing manufacturing cost and complexity
2Quantity of substance
If three-dimensional capacitors are used in dynamic random access memory cells, then storage capacity is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent removes the three-dimensional capacitor from the manufacturing process entirely. The data storage function is achieved through a floating diffusion region that can be formed using standard planar fabrication processes, eliminating the need for complex 3D capacitor manufacturing steps
Solution Approach 2:
The patent changes the fundamental approach to data storage from physical 3D capacitor structures to electrical charge storage in a floating diffusion region. This parameter change allows using conventional fabrication processes rather than complex 3D stacking processes, simplifying manufacturing
3Area of stationary object
If conventional dynamic random access memory cells are used, then area usage is reduced, but integration in system-on-chip applications is hindered due to process complexity
Solution Approach 1:
The patent extracts the problematic three-dimensional capacitor component that causes process complexity. By using a floating diffusion region with read and write transistors, the memory cell achieves compact area while being compatible with standard semiconductor fabrication processes suitable for system-on-chip integration
Solution Approach 2:
The patent creates a memory cell architecture that serves multiple functions: data storage, non-destructive read operation, and compact integration. The floating diffusion region acts as both the storage node and the interface for read/write operations, reducing the number of separate components needed and simplifying integration
4Area of stationary object
If three-transistor configuration with shared bit lines is used, then area requirements are reduced, but device complexity increases
Solution Approach 1:
The patent merges the read and write operations through shared bit lines. The same bit line infrastructure is used for both reading and writing data, reducing the number of separate interconnect structures needed and thereby reducing area requirements while maintaining functionality through careful circuit design
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for high-density integration with access speeds comparable to SRAM cells while reducing production costs and area requirements, enabling integration in system-on-chip applications.
Implementation Method 1
complementary field-effect transistor configuration
Data Source
AI summary
A semiconductor device includes a memory cell including a first transistor, a second transistor, and a third transistor. The first transistor has a first gate terminal and the second transistor has a second gate terminal, the first gate terminal and the second gate terminal being connected to a first word line and a second word line, respectively. The first transistor has a pair of first source/drain terminals and the second transistor has a pair of second source/drain terminals, one of the pair of first source/drain terminals and one of the pair of second source/drain terminals being connected to a common bit line. The third transistor has a third gate terminal connected to the other of the pair of first source/drain terminals, and a pair of third source/drain terminals connected to the other of the pair of second source/drain terminals and a supply voltage, respectively.