3T Memory Ferroelectric Gate Structure for Faster Switching
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Solution Overview
Problem
Conventional 3T DRAM transistors have limited switching speeds and data retention times due to the use of non-ferroelectric gate oxides, leading to issues with subthreshold swing and gate leakage.
Innovation Solution
Incorporating ferroelectric materials into the gate structures of 3T DRAM transistors to create FeFETs and NCFETs, which provide selectable permanent polarization or negative gate capacitance, enhancing data retention and switching speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional non-ferroelectric gate oxides are used in 3T DRAM transistors, then the device structure is simple and manufacturing is easier, but the switching speed is limited and data retention time is short
Solution Approach 1:
The patent changes the physical and chemical parameters of the gate oxide material by transitioning from conventional non-ferroelectric materials to ferroelectric materials. This parameter change enables permanent polarization states that significantly improve switching speed and data retention time, directly resolving the speed limitation while accepting increased structural complexity
Solution Approach 2:
The patent employs composite gate structures that integrate ferroelectric materials with conventional semiconductor materials. This composite approach combines the beneficial properties of ferroelectric materials (permanent polarization, fast switching) with the成熟的 processing compatibility of conventional materials, achieving improved performance while managing complexity
2Duration of action of moving object
If conventional non-ferroelectric gate oxides are used in 3T DRAM transistors, then the gate structure is simpler, but data retention time is limited
Solution Approach 1:
The patent changes the material parameter from non-ferroelectric to ferroelectric gate oxide, which fundamentally alters the data retention mechanism. The ferroelectric material's ability to maintain permanent polarization states without power enables extended data retention time, directly addressing the retention limitation while introducing structural complexity
Solution Approach 2:
The patent replaces the conventional capacitive storage mechanism with a ferroelectric polarization-based storage mechanism. This substitution eliminates the need for continuous refresh operations, significantly extending data retention time while accepting the complexity of integrating ferroelectric materials into the existing transistor structure
3Productivity
If conventional transistors are used, then manufacturing is easier, but write and read speeds are limited
Solution Approach 1:
The patent changes the gate oxide material parameter to ferroelectric, which fundamentally improves the switching characteristics and enables faster write and read operations. This parameter change directly enhances productivity by enabling rapid data operations, while the manufacturing process becomes more complex due to the specialized materials and processing steps required
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of FeFETs and NCFETs increases data retention times and switching speeds, potentially making the memory non-volatile and improving write and read speeds.
Implementation Method 1
Incorporating ferroelectric materials into the gate structures of 3T DRAM transistors to create FeFETs and NCFETs, which provide selectable permanent polarization
Implementation Method 2
Incorporating ferroelectric materials into the gate structures of 3T DRAM transistors to create FeFETs and NCFETs, which provide selectable permanent polarization or negative gate capacitance
Data Source
AI summary
A memory device including a plurality of memory cells, at least one of the plurality of memory cells includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first drain/source path and a first gate structure electrically coupled to a write word line. The second transistor includes a second drain/source path and a second gate structure electrically coupled to the first drain/source path of the first transistor. The third transistor includes a third drain/source path electrically coupled to the second drain/source path of the second transistor and a third gate structure electrically coupled to a read word line. Where, the first transistor, and/or the second transistor, and/or the third transistor is a ferroelectric field effect transistor or a negative capacitance field effect transistor.