3T OTP Memory Cell With Split Threshold Read Transistors

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Solution Overview

Problem

Current one-time programmable nonvolatile semiconductor memory devices require large transistors or devices to handle high program currents due to the use of poly or metal fuses, resulting in larger memory cells.

Innovation Solution

The implementation of a memory device with three transistors (3T or 1P2R) where one transistor is programmable and the other two are readout transistors, with the threshold voltage of one readout transistor being lower than the other, allowing for stable program and read currents by using a specific CAD layer to adjust dopant concentration and gate dielectric thickness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If poly or metal fuses are used to form one-time programming memory cells, then nonvolatile data storage is achieved, but large program current is required resulting in large memory cell size

Engineering Contradiction:
Improvenonvolatile data storageVSAvoidmemory cell size
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent changes the electrical parameters of the transistors by adjusting dopant concentration and gate dielectric thickness to create different threshold voltages. This allows the memory cell to operate with lower program current by using the threshold voltage difference between transistors rather than relying on high current through fuses, thereby reducing memory cell size while maintaining nonvolatile storage capability

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent replaces the mechanical/fuse-based switching mechanism with a transistor-based threshold voltage mechanism. Instead of using poly or metal fuses that require large currents to change state, the invention uses transistors with different threshold voltages controlled by dopant concentration and gate dielectric properties, substituting the fuse mechanism with a field-effect transistor mechanism that operates at lower currents

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Power

If large transistors or devices are used to handle large program current, then sufficient program current capability is achieved, but memory cell size increases

Engineering Contradiction:
Improveprogram current capabilityVSAvoidmemory cell size
Core Design Contradiction:
PowerVSArea of stationary object

Solution Approach 1:

The patent applies local quality by creating transistors with different threshold voltages through localized variations in dopant concentration and gate dielectric thickness. The programmable transistor has different doping characteristics than the readout transistors, allowing each transistor to be optimized for its specific function while maintaining compact dimensions, thus achieving sufficient program current capability without increasing overall memory cell size

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration reduces the size of memory cells while maintaining stable programming and reading operations, increasing readout current and compensating for parasitic resistance, thereby improving the overall efficiency of the memory device.

Implementation Method 1

the gate dielectric layer of the third transistor is broken down such that a conductive path is formed between the channel region of the third transistor and the gate electrode

Methodology Applied
Scientific EffectDielectric breakdown:

Implementation Method 2

a specific CAD layer to adjust dopant concentration and gate dielectric thickness

Methodology Applied
Scientific EffectDoping: Dopants

Data Source

PatentUS11844209B2Memory cell and method of forming the memory cell
Publication Date: 2023.12.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11844209B2 patent drawing
  • US11844209B2 patent drawing
  • US11844209B2 patent drawing

AI summary

A memory cell includes: a first transistor, having a first diffusion region coupled to a bit line and a first gate electrode coupled to a first word line; a second transistor, having a second diffusion region coupled to the bit line and a second gate electrode coupled to a second word line; and a third transistor, having a third diffusion region coupled to a fourth diffusion region of the first transistor, a fifth diffusion region coupled to a sixth diffusion region of the second transistor, and a third gate electrode coupled to a third word line; wherein the first transistor is arranged to have a first threshold voltage, the second transistor is arranged to have a second threshold voltage, and the second threshold voltage is different from the first threshold voltage.