3T CMOS Image Sensor Pixel With Parametric Reset for Low Noise

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Solution Overview

Problem

CMOS image sensors with three-transistor pixels face challenges in reducing reset noise and maintaining low dark current, especially when pixel size is minimized for high-resolution and low-cost image sensors, as existing solutions require additional transistors and complex signal processing.

Innovation Solution

A parametric circuit is introduced that dynamically changes the capacitance of the charge detection node during reset and sensing cycles, using a voltage-dependent capacitor to reduce reset noise and a shallow p-type implant to quench interface states and minimize dark current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a standard 3T pixel circuit is used, then the pixel structure is simple and compact, but the reset noise is high due to fixed detection node capacitance

Engineering Contradiction:
Improvepixel structureVSAvoidreset noise
Core Design Contradiction:
Device complexityVSObject-generated harmful factors

Solution Approach 1:

The patent applies the dynamics principle by making the detection node capacitance variable rather than fixed. A control transistor (第五晶体管) is introduced to dynamically adjust the effective capacitance of the detection node during different operational phases. During reset phase, the capacitance is reduced to minimize kTC noise, while during signal integration phase, the capacitance is increased to improve signal sensitivity. This dynamic adjustment resolves the contradiction between simple structure and low reset noise.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the capacitance parameter of the detection node based on operational requirements. By controlling the fifth transistor to connect or disconnect additional capacitance, the detection node capacitance is adjusted between two states: a lower value during reset to reduce noise, and a higher value during signal accumulation to enhance sensitivity. This parameter change approach allows the same hardware structure to optimize performance for different operational phases without increasing overall device complexity.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the detection node capacitance is increased to improve signal sensitivity, then the dynamic range improves, but the reset noise increases

Engineering Contradiction:
Improvesignal sensitivityVSAvoidreset noise
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent resolves this contradiction by making the capacitance dynamic rather than static. The control transistor switches the capacitance value based on the operational phase: during reset, capacitance is minimized to reduce kTC noise (sqrt(kTC)); during signal integration, capacitance is maximized to improve signal sensitivity and dynamic range. This temporal separation of capacitance values allows optimization for both noise reduction and signal detection without compromise.

Inventive Principle:
Principle #15Dynamics

3Object-generated harmful factors

If additional transistors are added to reduce reset noise, then the noise performance improves, but the pixel area increases

Engineering Contradiction:
Improvereset noiseVSAvoidpixel area
Core Design Contradiction:
Object-generated harmful factorsVSArea of moving object

Solution Approach 1:

The patent applies multi-functionality by making the fifth transistor serve multiple purposes: it controls the detection node capacitance during reset phase to reduce noise, and also controls the capacitance during signal integration phase to optimize sensitivity. This single transistor performs what would traditionally require multiple separate components, thereby reducing reset noise without proportionally increasing pixel area. The control signal for the fifth transistor is derived from existing pixel control signals, further minimizing additional area requirements.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in a 3T pixel with reduced reset noise, high dynamic range, and low dark current, enabling compact, high-performance image sensors with simpler structures and reduced power consumption.

Implementation Method 1

By incorporating a voltage dependent 'parametric' capacitor component into the detection node achieves this goal and other objects of the invention

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

The low dark current generation is achieved by quenching the interface states by placing a p+ implant near the silicon-silicon dioxide interface

Methodology Applied
Scientific EffectInterface state quenching:

Implementation Method 3

A typical image sensor senses light by converting impinging photons into electrons that are integrated (collected) in sensor pixels

Methodology Applied
Scientific EffectPhotoelectric effect: Photoelectric Effect

Data Source

PatentUS8508638B23T pixel for CMOS image sensors with low reset noise and low dark current generation utilizing parametric reset
Publication Date: 2013.08.13 INTELLECTUAL VENTURES II LLC
  • US8508638B2 patent drawing
  • US8508638B2 patent drawing
  • US8508638B2 patent drawing

AI summary

The present invention describes in detail the solid-state image sensor, specifically the image sensors pixel that has three transistors, high sensitivity, low reset noise, and low dark current. Low reset noise is achieved by parametrically changing the voltage dependent capacitance of the charge detection node in such a manner that during reset the charge detection node capacitance is low while during sensing and integration cycles the charge detection node capacitance is high. This feature thus results in high dynamic range, which is important for sensors using very small pixels. The low dark current generation is achieved by quenching the interface states by placing a p+ implant near the silicon-silicon dioxide interface.