3T RAM Cell with FeFETs for Non-Volatile Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor memory devices, such as SRAM and DRAM, are volatile, requiring periodic refreshing and inefficient in terms of semiconductor substrate usage, necessitating a non-volatile memory solution that optimizes lateral footprint.
Innovation Solution
A three-transistor random access memory (3T RAM) cell utilizing ferroelectric-based field effect transistors (FeFETs) with separate read and write paths, along with a memory controller for specific voltage applications, is developed to create a non-volatile memory cell that reduces cell size and enhances power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SRAM or DRAM architectures are used, then memory capacity can be achieved, but the memory devices are volatile and require periodic refreshing
Solution Approach 1:
The patent changes the fundamental parameter of memory cell operation from volatile to non-volatile by introducing ferroelectric material in the gate dielectric of the FeFET. This material retains polarization state without continuous power supply, enabling non-volatile memory operation while maintaining the 3T cell architecture efficiency.
Solution Approach 2:
The patent replaces the conventional charge-based storage mechanism in DRAM with a polarization-based mechanism in FeFET. The ferroelectric material's spontaneous polarization replaces the need for continuous refreshing of charge, substituting a passive physical property for an active maintenance process.
2Area of stationary object
If conventional SRAM or DRAM architectures are used, then memory functionality is achieved, but efficient use of semiconductor substrate lateral footprint is not optimized
Solution Approach 1:
The patent segments the memory cell into three distinct transistor components (FeFET for storage, read transistor, write transistor) with separate read and write paths. This segmentation allows independent optimization of each component's function while achieving compact integration that reduces overall lateral footprint compared to conventional architectures.
Solution Approach 2:
The FeFET serves multiple functions: it acts as both the storage element (replacing the capacitor in DRAM) and the switch element. This multi-functionality reduces the total component count and lateral area required compared to conventional 6T SRAM or 3T DRAM cells.
3Power
If the gate oxide thickness of the third transistor is increased to sustain double gate electrical field, then the transistor can withstand higher supply voltage, but the device complexity increases
Solution Approach 1:
The patent applies different gate oxide thicknesses to different transistors within the same memory cell based on their specific functional requirements. The third transistor (write transistor) has thicker gate oxide to withstand higher voltages during write operations, while other transistors use thinner oxide for lower voltage operation, optimizing each component locally.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 3T RAM cell with FeFETs provides low-power, non-volatile memory capabilities, eliminating the need for refreshing and optimizing the use of semiconductor substrate space, while simplifying control circuits and reducing power consumption.
Implementation Method 1
the ability of the ferroelectric material to retain its polarization in the absence of an electric field
Implementation Method 2
the gate oxide thickness of the third transistor is larger than the gate oxide thickness of the second transistor such that the third transistor is adapted to sustain a double gate electrical field
Data Source
AI summary
The disclosed technology is generally directed to semiconductor integrated circuit devices and more particularly to a three-transistor random access memory (3T RAM) device, and a method of fabricating and operating the same. In one aspect, a 3T RAM cell includes a ferroelectric-based field effect transistor (FeFET) having a first gate connected as a storage node and a second transistor connected between the FeFET and a read bit line having a second gate connected to a read word line. The 3T RAM cell also includes a third transistor connected between the storage node and a write bit line having a third gate connected to a write word line.