3T2C Non-Volatile Memory Cell Erase Voltage Stress Reduction
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Solution Overview
Problem
Conventional non-volatile memory cells, particularly those with a 2T1C structure, face challenges in efficiently performing erase actions without subjecting electronic components in the erase line driver to high voltage stress, which can lead to component damage.
Innovation Solution
The proposed solution involves a novel memory cell architecture referred to as a 3T2C structure, which includes a select transistor, a floating gate transistor, a switching transistor, and two capacitors. This configuration allows for the ejection of hot carriers from the floating gate during an erase action without requiring the erase line driver to provide the highest erase voltage, thereby reducing voltage stress on electronic components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the erase line driver provides the highest erase voltage to perform erase actions, then the erase operation effectiveness is improved, but the voltage stress on electronic components increases leading to potential damage
Solution Approach 1:
The erase voltage generation is segmented into two parts: a first voltage (e.g., 7.5V) provided by the erase line driver to the erase line, and a second voltage (e.g., 7.5V) provided by a booster circuit to the first capacitor. The combination of these two voltages through the capacitor achieves the required high erase voltage (e.g., 15V) without subjecting the erase line driver to the full voltage stress, thereby improving component reliability while maintaining effective erase operations.
2Device complexity
If a conventional 2T1C memory cell structure is used, then the device complexity is reduced, but the ability to perform erase actions without high voltage stress on components is limited
Solution Approach 1:
The invention embeds additional functional elements within the memory cell structure: a first capacitor is added with its first terminal connected to the floating gate of the memory transistor and its second terminal connected to the erase line, and a second capacitor is added with its first terminal connected to the erase line and its second terminal connected to the bit line. This nested addition of capacitors enables the voltage stacking function while maintaining a relatively compact cell structure, achieving component protection during erase operations.
3Productivity
If the erase voltage is transmitted through the erase line driver switching paths, then the erase action is enabled, but the electronic components in the switching paths are subjected to highest voltage stress
Solution Approach 1:
The first capacitor serves as an intermediary element that couples the floating gate to the erase line. During erase operations, the capacitor blocks direct DC current flow while allowing the voltage signal to be transmitted, thereby enabling the erase action without subjecting the erase line driver and its switching paths to the full high voltage stress. The capacitor acts as a mediator that transmits the necessary voltage signal while protecting the driving circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 3T2C memory cell architecture enables effective erase operations without subjecting electronic components to the highest voltage stress, thereby enhancing the reliability and longevity of the non-volatile memory system.
Implementation Method 1
a first capacitor, and a second capacitor. A first terminal of the first capacitor is connected with a floating gate of the first floating gate transistor. A second terminal of the first capacitor is connected with a first erase node. A first drain/source terminal of the first switching transistor is connected with the first erase node. A second drain/source terminal of the first switching transistor is connected with a first erase line. A gate terminal of the first switching transistor is connected with a control line. A first terminal of the second capacitor is connected with the first erase node. A second terminal of the second capacitor is connected with a first boost line.
Data Source
AI summary
A memory cell of a non-volatile memory includes a select transistor, a floating gate transistor, a first capacitor, a switching transistor and a second capacitor. A first drain/source terminal of the select transistor is connected with a source line. A gate terminal of the select transistor is connected with a word line. The two drain/source terminals of the floating gate transistor are respectively connected with a second drain/source terminal of the select transistor and a bit line. The first capacitor is connected between a floating gate of the floating gate transistor and an erase node. The two drain/source terminals of the switching transistor are respectively connected with the erase node and an erase line. The gate terminal of the switching transistor is connected with a control line. The second capacitor is connected between the erase node and a boost line.