4F2 DRAM Contact Structure With Self-Aligned Metallized Junctions
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Solution Overview
Problem
The 4F2 DRAM cell architecture faces challenges such as the floating body effect and difficulties in forming bit line or storage node contacts due to the isolation of the channel from the body, which complicates the formation of these contacts and affects the area density and efficiency of the memory array.
Innovation Solution
The solution involves forming a substrate with a unique orientation, where a sacrificial material is removed after frontside processing to create a void that is then filled with a metallized material, allowing for self-aligned formation of bit lines or storage node contacts without the need for complex masking and etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the channel is isolated from the body in 4F2 DRAM architecture, then area density is improved, but formation of bit line or storage node contacts becomes difficult
Solution Approach 1:
The patent applies preliminary action by forming the bit line or storage node contact junctions with the channel before the channel is isolated from the body. This sequence allows direct contact formation when the channel is still connected to the body, avoiding the difficulty of forming contacts through the isolated channel structure later. The junctions are created in an early process stage when manufacturing is easier, then the channel isolation is performed subsequently.
2Ease of manufacture
If complex masking and etching processes are used to form bit line or storage node contacts, then contact formation is achieved, but process complexity and cost increase
Solution Approach 1:
The patent performs contact junction formation as a preliminary action before channel isolation, when simpler processes can be used. By establishing the electrical connections early in the fabrication sequence, the need for complex subsequent masking and etching operations to create contacts through isolated structures is eliminated, reducing overall process complexity.
Solution Approach 2:
The patent inverts the conventional sequence by forming contacts before isolation rather than after. This reversal of the typical manufacturing sequence allows for simpler contact formation processes, avoiding the need for complex etching and masking operations that would be required if contacts were formed after the channel was isolated.
3Reliability
If standard doping processes are used for source/drain regions, then doping is achieved, but resistivity control and alignment precision are insufficient
Solution Approach 1:
The patent applies local quality by implementing tailored doping processes for source/drain regions with spatially varying dopant concentrations. Different doping levels and profiles are applied to different locations within the source/drain regions, allowing precise control of resistivity in specific areas. This localized doping approach enables optimization of electrical properties where needed while maintaining manufacturing precision through the self-aligned nature of the process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the complexity and cost of forming bit line or storage node contact junctions, achieves higher quality junctions for 4F2 DRAM devices, and allows for tailored doping of source/drain regions, resulting in improved resistivity and alignment of the metallized features.
Implementation Method 1
one or more first epitaxially grown junction material layers formed over the sacrificial layer, an epitaxially grown channel material formed over the first junction material, and one or more second epitaxially grown junction material layers formed over the channel material
Data Source
AI summary
The present technology includes vertical cell dynamic random-access memory (DRAM) arrays with improve bit line and storage node contact resistivity and self-alignment as well as methods of making such arrays. The arrays include a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The arrays include a plurality of channels extending in a vertical direction that is generally orthogonal to the first direction and the second horizontal direction, such that the plurality of bit lines intersect with a source/drain region of the plurality of channels, and the plurality of word lines intersect with gate regions of the plurality of channels. In addition, arrays include where a bit line, a storage node contact, or both, are formed from a metallized material.