4T Memory Cell Layout for Lower Resistance in Dense Memory Arrays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor integrated circuits (ICs) become smaller and more complex, the resistance of conductive lines within digital devices affects operating voltages and overall IC performance, particularly in memory macros.
Innovation Solution
A memory cell design incorporating a first and second pull up transistor, a first and second pass gate transistor, and a first metal contact, with specific layout patterns for active regions, gates, and conductive features to enhance connectivity and reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conductive lines are made thinner to increase density, then device density improves, but resistance increases affecting operating voltages and performance
Solution Approach 1:
The patent combines multiple conductive lines into a shared trench structure, allowing multiple bit lines or word lines to occupy the same physical space. This merging approach increases device density while maintaining adequate conductive cross-section area to control resistance, as the combined structure provides multiple parallel conduction paths.
Solution Approach 2:
The patent transitions from planar conductive line arrangement to three-dimensional stacked architecture by forming conductive lines at different depths within trenches. This vertical dimensionality change allows higher density without proportionally reducing the horizontal conductive width, thereby maintaining lower resistance while increasing capacity.
2Quantity of substance
If conductive lines are made thinner to increase density, then device density improves, but operating voltages are affected
Solution Approach 1:
Multiple conductive lines are merged into shared trenches with common fill material, creating parallel conduction paths that reduce overall resistance. This maintains adequate current carrying capacity and voltage stability while achieving higher density through improved spatial utilization.
Solution Approach 2:
The patent employs composite conductive structures combining different materials (e.g., copper fill with dielectric surrounding, or multi-layer conductive compounds) to achieve both high density and low resistance. The composite structure optimizes electrical properties while minimizing voltage drops in high-density configurations.
3Quantity of substance
If more conductive lines are packed closer together, then device density improves, but resistance increases
Solution Approach 1:
Adjacent conductive lines are merged into shared trenches, ensuring uniform spacing and consistent electrical properties. This merging approach maintains reliable electrical connectivity through controlled impedance and resistance while maximizing the number of lines per unit area.
Solution Approach 2:
The patent applies different material properties and structural characteristics to specific regions of the conductive network. Local optimization of conductive fill material, trench depth, and cross-sectional area ensures that each conductive line maintains appropriate electrical characteristics for reliable operation, even in high-density packed arrangements.
Data Source
AI summary
A memory circuit includes a word line, a bit line, a bit line bar, a first and second pull up transistor coupled to a voltage supply, a first and second pass gate transistor, a first and second active region and a first contact. The first active region is an active region of at least one of the first or the second pull up transistor. The second active region is an active region of the first or the second pass gate transistor. The first contact extending from the first active region to the second active region, and electrically coupling a drain of the first pull up transistor to a drain of the first pass gate transistor. The first pass gate transistor, the second pass gate transistor, the first pull up transistor and the second pull up transistor are part of a four transistor (4T) memory cell.