4T SRAM Cell Layout With Resistive Load for 28 nm Scaling
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Solution Overview
Problem
The challenge of miniaturizing SRAM cells to 28 nm or lower is exacerbated by increased area due to interference among contacts, metal wire layouts, and parasitic junctions, leading to larger die sizes and potential latch-up issues, which affect storage density, power consumption, and yield.
Innovation Solution
A 4T SRAM cell structure is designed with resistive load MIM structures replacing PMOS transistors, utilizing dielectric layers and tunneling effects to maintain area size, and incorporating superlattice structures for current conduction, reducing the SRAM cell size to 51λ² while minimizing parasitic effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If traditional 6T SRAM cell structure is used with multiple interconnection layers, then signal transmission is facilitated, but the total area of the SRAM cell dramatically increases when minimum feature size decreases
Solution Approach 1:
The patent transitions from planar interconnection to vertical 3D stacking architecture. Multiple interconnection layers (M1, M2, M3) are stacked vertically with vias connecting them, allowing signal transmission in the vertical dimension rather than expanding horizontally. This reduces theSRAM cell footprint from λ² to a smaller area while maintaining multi-layer interconnection capabilities.
Solution Approach 2:
The patent implements nested interconnection structures where M2 and M3 layers are positioned above M1 layer, with vias nesting through multiple layers. The gate and diffusion regions are nested within the vertical stack, with contacts and vias nested sequentially from bottom to top, maximizing space utilization and reducing lateral area.
2Quantity of substance
If minimum feature size is reduced to increase storage density, then more cells fit on chip, but process variations in transistor performance increase
Solution Approach 1:
The patent changes the transistor architecture from planar to vertical FinFET structure. The fin height (vertical dimension) becomes the effective channel length, decoupling it from the lateral minimum feature size. This allows storage density to scale with lateral dimensions while transistor performance is controlled by vertical fin geometry, reducing process variation impact.
Solution Approach 2:
The patent moves transistor channel from 2D planar to 3D vertical FinFET structure. The channel extends vertically as a fin, providing better gate control and reduced short-channel effects. This dimensional transition allows independent optimization of density (lateral) and performance (vertical), mitigating process variation issues at scaled dimensions.
3Area of stationary object
If SRAM cell is miniaturized to reduce die size, then storage density increases, but latch-up issues due to parasitic junctions become more severe
Solution Approach 1:
The patent separates n-type and p-type transistor fins into different vertical levels or spatial positions within the 3D structure. This vertical separation increases the distance between parasitic n-p-n-p junctions, raising latch-up trigger voltage and reducing susceptibility. The harmful parasitic paths are disrupted by the three-dimensional spatial arrangement.
Solution Approach 2:
The patent introduces shallow trench isolation (STI) structures as intermediary elements between n-type and p-type regions. The STI acts as a physical barrier that increases the distance between parasitic junctions and provides electrical isolation, preventing latch-up conditions while allowing compact cell design.
4Adaptability or versatility
If complex interconnection structures with multiple via layers are used, then connectivity is improved, but manufacturing complexity and difficulty increase
Solution Approach 1:
The patent performs preliminary self-alignment of vias to contacts during the fabrication process. The via formation is pre-aligned to contact positions using self-aligned processes, eliminating the need for separate alignment steps and reducing manufacturing complexity. This preliminary positioning action simplifies the overall fabrication sequence.
Solution Approach 2:
The patent merges multiple interconnection functions into a unified 3D stacked architecture. The vertical stack combines power supply, signal transmission, and grounding functions in a single integrated structure, reducing the number of separate components and simplifying manufacturing compared to planar alternatives.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The new design maintains SRAM cell area at acceptable levels, reduces parasitic junction noise, and enhances yield by using dielectric materials like hBN for temperature-insensitive current conduction, achieving compact bit cell sizes and stable signal margins.
Implementation Method 1
utilizing dielectric layers and tunneling effects to maintain area size
Data Source
AI summary
A SRAM cell structure includes a plurality of transistors, a set of contacts, a word-line, a bit-line, a VDD contacting line and a VSS contacting line. The plurality of transistors include n transistors, wherein n is a positive integral less than 6. The set of contacts are coupled to the plurality of transistors. The word-line is electrically coupled to the plurality of transistors. The bit-line and a bit line bar are electrically coupled to the plurality of transistors. The VDD contacting line is electrically coupled to the plurality of transistors. The VSS contacting line is electrically coupled to the plurality of transistors. Wherein as a minimum feature size of the SRAM cell structure gradually decreases from 28 nm, an area size of the SRAM cell in terms of square of the minimum feature size (λ) is the same or substantially the same.