4T2C NVM Cell Structure for Gate Dielectric Reliability
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Solution Overview
Problem
Multi-time programmable (MTP) cells in non-volatile memory (NVM) experience device failure and reduced reliability due to damage to the gate dielectric structure during programming operations, leading to inaccurate read operations and limited endurance.
Innovation Solution
A four-transistor-two-capacitor (4T2C) configuration memory cell design is introduced, where the programming operation isolates Fowler-Nordheim tunneling from the bit line read active region, preventing damage to the gate dielectric structure and enhancing the number of programmable operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional MTP cell programming operations are performed, then data can be stored in non-volatile memory, but the gate dielectric structure becomes damaged leading to device failure and reduced reliability
Solution Approach 1:
The patent divides the bit line functionality into separate active regions: a first bit line active region for programming operations and a second bit line active region for read operations. This segmentation prevents the harmful Fowler-Nordheim tunneling effects during programming from affecting the read region, thereby protecting the gate dielectric structure and improving reliability
Solution Approach 2:
The patent introduces an intermediate structure (the isolation structure with different doping types) between the first and second bit line active regions. This intermediary prevents the propagation of harmful effects from the programming region to the read region, acting as a protective barrier that maintains gate dielectric integrity
2Duration of action of moving object
If programming operations are performed on MTP cells, then data storage capability is achieved, but the number of programmable operations is limited due to endurance issues
Solution Approach 1:
By segmenting the bit line operations into separate active regions, the patent enables the read region to remain unaffected by programming operations. This allows for a greater number of programming cycles to be performed before device failure occurs, thereby increasing endurance
Solution Approach 2:
The patent converts the potentially harmful Fowler-Nordheim tunneling effects into a beneficial isolation mechanism. The tunneling that occurs during programming in the first active region is contained and prevented from reaching the second active region, allowing aggressive programming operations without compromising long-term reliability
3Productivity
If programming operations are performed using Fowler-Nordheim tunneling, then data can be programmed into the memory cell, but inaccurate read operations occur due to gate dielectric damage
Solution Approach 1:
The patent segments the bit line functionality into dedicated programming and reading regions, ensuring that the harmful effects of Fowler-Nordheim tunneling during programming do not interfere with read operations. This maintains both programming productivity and read accuracy
Solution Approach 2:
The isolation structure acts as an intermediary barrier that prevents the degradation of gate dielectric in the read region caused by programming operations. This ensures that read operations remain accurate even after multiple programming cycles
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 4T2C configuration increases the endurance and reliability of the memory cell by mitigating damage to the gate dielectric structure, reducing inaccurate read operations, and allowing for more program and erase cycles without adverse effects on read operations.
Implementation Method 1
programming operation isolates Fowler-Nordheim tunneling from the bit line read active region
Data Source
AI summary
Various embodiments of the present disclosure are directed towards an integrated chip including a first well region and a second well region disposed within a substrate. A gate electrode overlies the first well region and the second well region. A first memory active region is disposed within the second well region. A second memory active region is disposed within the second well region and is laterally offset from the first memory active region by a non-zero distance.