5B/6B Coding Circuit for DC Balance at High Data Rates
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Solution Overview
Problem
Conventional circuit arrangements for five bit/six bit coding and decoding are limited by the cumulative run times of digital gates, preventing high-coded data transfer rates.
Innovation Solution
A circuit arrangement comprising half-adders, full-adders, NOR gates, AND gates, and a buffer, which determines specific information about the input bits to encode them into six-bit output bits, ensuring direct current balance and neutrality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional circuit arrangements with multiple digital gates are used for 5b/6b coding, then the coding function is achieved, but the cumulative gate run times prevent high coded data transfer rates
Solution Approach 1:
The patent divides the 5b/6b coding function into two independent parallel paths: a combinatorial logic path that generates code words based on input bit patterns, and a disparity control path that manages DC balance. This segmentation allows simultaneous execution of coding and disparity management without sequential gate delays accumulating, thereby increasing the coded data transfer rate while reducing the effective time loss from gate operations.
2Reliability
If DC-balanced signaling is implemented through traditional coding methods, then signal neutrality is achieved, but the circuit complexity and gate delays limit transfer speed
Solution Approach 1:
The patent implements preliminary action by pre-defining disparity states and pre-calculating the required adjustments for maintaining DC balance. The disparity control logic is prepared in advance with lookup tables and pre-computed correction patterns, allowing the coding circuit to maintain DC balance without adding sequential processing delays. This preliminary preparation enables the system to achieve both reliability through DC balance and high productivity through parallel operation.
Data Source
AI summary
A circuit arrangement for determining and providing a first information I1−, that in a digital input word A B C D E comprising a first input bit A, a second input bit B, a third input bit C, a fourth input bit D and a fifth input bit E, at most only one of the five input bits A, B, C, D, E comprises the value 1 (“high”), a second information I2, that in the input word A B C D E exactly two of the five input bits A, B, C, D, E comprise the value 1 (“high”), a third information I3, that in the input word A B C D E exactly three of the five input bits A, B, C, D, E comprise the value 1 (“high”) and a fourth information I4+, that in the input word A B C D E at least four of the five input bits A, B, C, D, E comprise the value 1 (“high”).