Five-Dimensional Torus Network for Supercomputer Scalability
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Solution Overview
Problem
Current supercomputing architectures face challenges with increasing memory latency and high power density, limiting their scalability and efficiency in achieving high performance at 100 petaflop scales.
Innovation Solution
A novel massively parallel supercomputer architecture utilizing System-On-a-Chip technology with a five-dimensional torus network and direct memory access interface, integrating multiple processors on a single ASIC to minimize latency and optimize packet communications, while enabling adaptive partitioning of processors for efficient computation and communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If standard processors configured in SMP configurations are used to build supercomputers, then computing performance can be achieved at 1-3 petaflops, but memory latency increases and power density becomes high, limiting scalability to 100 petaflop scales
Solution Approach 1:
The system segments processing into compute nodes and I/O nodes, with each node containing multiple processing elements (PEs) that can be independently configured. This segmentation allows the system to scale to 100 petaflops by adding more nodes rather than increasing the scale of individual SMP configurations, thereby reducing power density per node while maintaining overall system performance.
Solution Approach 2:
The patent introduces a five-dimensional torus network interconnection that adds dimensional complexity to the system architecture. This multi-dimensional interconnection topology provides more efficient communication paths compared to traditional SMP interconnects, reducing memory access latency and enabling scalable performance at 100 petaflop scales without proportionally increasing power consumption.
2Productivity
If the number of processing nodes is increased to achieve higher performance, then computing power increases, but the distance to memory increases causing higher latency
Solution Approach 1:
The architecture implements nested memory hierarchies within each processing element, with local caches and memory structures organized in multiple levels. This nesting allows frequently accessed data to be stored closer to the processing elements, reducing memory access latency even as the overall system scales to hundreds of petaflops of computing power.
Solution Approach 2:
The patent introduces DMA (Direct Memory Access) controllers and buffer memory structures as intermediaries between processing elements and main memory. These intermediaries allow data transfer to occur in parallel with computation, hiding memory access latency and enabling sustained high computing power without proportionally increasing memory access time.
3Speed
If multiple processors are integrated on a single ASIC, then latency is minimized and communication is optimized, but device complexity increases
Solution Approach 1:
The processing elements within each ASIC are designed with universal, standardized interfaces and functional units that can perform multiple operations. This multi-functionality reduces the overall complexity of the ASIC by using repeated modular blocks rather than custom-circuitry for each function, while still achieving high communication speed through optimized inter-PE connections.
Solution Approach 2:
The patent employs configurable parameters within the ASIC design that allow the same hardware structure to adapt to different computational requirements. This configurability reduces design complexity by using parameterized modules rather than fixed-function circuits, enabling high-speed communication across multiple processors while managing ASIC integration complexity through systematic design reuse.
Data Source
AI summary
A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.