Modular 5G UE Layer-2 Data Stack for High-Throughput Low-Latency
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Solution Overview
Problem
Traditional 3GPP Layer-2 data stacks are tightly coupled with protocol stacks of the physical layer and control plane, lacking a clear distinction between functional partitions, which hinders the design of data path architectures required for high throughput and extreme low latency data packet applications in 5G modems, and require high-cost processors with complex software designs.
Innovation Solution
A customizable and programmable 5G user equipment (UE) layer-2 data stack solution implemented in the data plane, utilizing data plane hardware, a data plane microcontroller, or a combination thereof, with APIs for communication across different layers, enabling flexible and efficient data packet operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional 3GPP Layer-2 data stacks are used with tight coupling to protocol stacks, then system stability is maintained, but data throughput is limited and latency cannot be reduced to extreme levels
Solution Approach 1:
The patent segments the Layer-2 data stack into separate functional modules (MAC layer, RLC layer, PDCP layer, SDAP layer) that can be independently configured and processed. This modular segmentation allows specific layers to be optimized for high throughput while others handle control functions, resolving the contradiction between productivity and device complexity by enabling selective hardware acceleration without requiring complete redesign of the entire protocol stack
Solution Approach 2:
The patent introduces a data plane micro controller as an intermediary component that mediates between the control plane and data plane hardware. This intermediary manages the separation between control and data functions, allowing the data plane to operate independently at high speeds while the control plane handles protocol management, thus achieving high throughput without proportionally increasing overall system complexity
2Productivity
If high-cost processors with complex software designs are used, then high throughput can be achieved, but cost increases and system complexity worsens
Solution Approach 1:
The patent replaces complex software-based protocol processing with dedicated hardware modules for specific Layer-2 functions. By implementing MAC, RLC, PDCP, and SDAP layers as configurable hardware blocks rather than software routines, the system achieves high throughput through hardware acceleration while reducing the need for expensive high-performance general-purpose processors, thereby lowering manufacturing costs
Solution Approach 2:
The patent designs universal hardware modules that can be configured to perform different Layer-2 functions through programmable interfaces. These multi-functional blocks can be dynamically allocated based on traffic requirements, allowing a single hardware design to support multiple protocol variations and service types, thus reducing the need for multiple specialized components and lowering overall manufacturing cost
3Loss of time
If traditional tightly coupled protocol stacks are used, then implementation simplicity is maintained, but latency cannot be reduced to extreme levels required for 5G applications
Solution Approach 1:
The patent segments the data path into separate processing stages corresponding to different Layer-2 protocols, with each segment handled by dedicated hardware modules. This segmentation enables parallel processing of different protocol functions simultaneously, reducing the sequential processing time that causes latency in traditional coupled architectures, while the modular structure manages complexity through clear interface definitions
Solution Approach 2:
The patent implements preliminary action by pre-configuring hardware modules with protocol parameters and processing rules before data arrival. The data plane micro controller pre-loads configuration data and prepares processing pipelines in advance, allowing data packets to be processed immediately upon arrival without configuration delays, thus reducing latency while maintaining manageable complexity through upfront preparation
4Productivity
If clear functional partitioning is implemented across layers, then high throughput and low latency are achieved, but adaptability to different customer needs decreases
Solution Approach 1:
The patent implements dynamic configurability where hardware modules can be programmatically adjusted to change their processing behavior. The data plane micro controller and APIs allow runtime reconfiguration of protocol parameters, buffer sizes, and processing priorities based on customer requirements, enabling the same hardware architecture to adapt to different throughput and latency needs while maintaining the functional partitioning that enables high performance
Data Source
AI summary
Methods for providing a layer-2 data stack solution in a data plane and associated devices are provided. In some embodiments, the method includes (i) determining, among a plurality of data stack solutions that are selectable, which layer-2 data stack solution is selected and (ii) causing, according to the selected layer-2 data stack solution, the layer-2 micro controller to intervene with a data plane hardware module that is configured to implement a specific layer-2 data stack function. Each of the plurality of data stack solutions represents a distinctive intervening configuration of a layer-2 micro controller. The layer-2 micro controller is coupled to a number of data plane hardware modules that are configured to implement different layer-2 data stack functions. The intervening configuration of the layer-2 micro controller is indicative of a level of control of the layer-2 micro controller over the data plane hardware modules.