5G Uplink Symbol Multiplexing With ASIC Mapping Acceleration
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Solution Overview
Problem
Existing 3GPP 5G NR uplink communication systems face challenges in efficiently multiplexing Uplink Control Information (UCI) bits and data bits with Demodulation Reference Symbols (DMRS) and Phase Tracking Reference Symbols (PTRS) due to complex calculations unsuitable for ASIC implementation, leading to high processing latency.
Innovation Solution
A network system comprising a processor, accelerator, and modulation controller performs symbol-based multiplexing and resource mapping, using an ASIC hardware accelerator to calculate mapping parameters and avoid reserved locations for PTRS, enabling efficient symbol-by-symbol task allocation and reduced latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If straightforward implementation of 3GPP specification algorithms is used for multiplexing UCI and data bits, then multiplexing functionality is achieved, but processing latency increases and implementation complexity becomes unsuitable for ASIC
Solution Approach 1:
The patent segments the multiplexing process into distinct functional blocks: UCI bit sequence generation, data bit sequence generation, separate bit sequence multiplexing, and resource element mapping. Each block processes specific portions of the data independently, enabling parallel processing and reducing overall latency while maintaining specification compliance.
Solution Approach 2:
The patent performs preliminary calculations of mapping parameters and resource element allocations before the actual multiplexing operation. By pre-determining which resource elements will carry UCI versus data bits, the system avoids complex real-time decision-making during transmission, thereby reducing processing latency suitable for ASIC implementation.
2Manufacturing precision
If complex calculation algorithms from 3GPP specification are implemented, then accurate multiplexing is achieved, but resource requirements increase and latency increases
Solution Approach 1:
The patent extracts the computationally intensive calculation components from the overall multiplexing process and implements them as separate, optimized functional blocks. By isolating the complex mapping parameter calculations from the bit sequence multiplexing operations, the system maintains accuracy while reducing overall resource requirements through specialized processing paths.
Solution Approach 2:
The patent transforms the multiplexing problem by changing the parameter representation and calculation methods. Instead of implementing the full specification algorithms directly, it uses alternative parameter calculations that achieve the same multiplexing accuracy with reduced computational complexity, making the system suitable for resource-constrained ASIC implementations.
3Loss of time
If symbol-by-symbol task allocation is implemented, then processing latency is reduced, but implementation complexity increases
Solution Approach 1:
The patent divides the processing tasks into symbol-level segments where each OFDM symbol is processed independently with dedicated task allocation. This segmentation enables parallel processing across multiple symbols, significantly reducing processing latency while keeping each individual symbol's task allocation relatively simple and manageable.
Data Source
AI summary
Methods and apparatus for symbol-to-symbol multiplexing of control, data, and reference signals on a 5G uplink. In one aspect, a job descriptor generator is configured to calculate mapping parameters for each symbol based on high level configuration parameters. A data/UCI multiplexing job engine, which is coupled to the job descriptor generator, provides symbol-based multiplexing and mapping which includes calculating reserved locations for PTRS and DMRS based on frequency-domain mapping of both PTRS and DMRS and multiplexing of data and controls from calculated intermediate parameters. A downstream processor is coupled to the job engine and configured to modulate data and control REs and insert DMRS or PTRS. In one example, the job descriptor generator is a configurable DSP processor and the job engine is an ASIC hardware accelerator.