5T SRAM Cell Voltage Control for Stability and Power
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Solution Overview
Problem
Conventional 5T SRAM circuits suffer from read instability, low writeability, and larger layout size due to process variation and unbalanced transistor sizing, which affects stability and writability, especially in deep submicron technologies.
Innovation Solution
The proposed 5T SRAM architecture features balanced transistor sizing, a single access transistor, and control logic to adjust cell voltage during write operations, reducing cell voltage and increasing access transistor size, thereby improving writeability and stability while maintaining a smaller layout size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional 6T SRAM architecture is used, then read stability is maintained, but power consumption increases and layout size increases
Solution Approach 1:
The patent removes one access transistor from the conventional 6T SRAM structure to create a 5T SRAM cell. This extraction of the redundant access transistor reduces the transistor count from six to five, thereby reducing static power consumption while maintaining read stability through the single access transistor's optimized design
Solution Approach 2:
The patent modifies the threshold voltage parameter of the single access transistor to optimize its behavior. By adjusting the threshold voltage, the access transistor achieves proper switching characteristics that maintain read stability while enabling lower power consumption compared to the conventional 6T structure
2Reliability
If conventional 6T SRAM architecture is used, then read stability is maintained, but layout size increases
Solution Approach 1:
The patent extracts and removes one access transistor from the conventional 6T SRAM structure, reducing the transistor count from six to five. This reduction directly decreases the layout area while maintaining read stability through the optimized single access transistor design
Solution Approach 2:
The patent merges the functions of two access transistors into a single access transistor by utilizing the complementary bit line structure. This merging reduces the number of components and simplifies the layout while maintaining the necessary read stability through proper transistor sizing and threshold voltage optimization
3Use of energy by moving object
If 5T SRAM architecture is used, then power consumption is reduced, but read stability deteriorates due to process variation
Solution Approach 1:
The patent optimizes the threshold voltage parameter of the single access transistor to compensate for process variations. By carefully selecting and adjusting the threshold voltage, the access transistor maintains stable reading operation across different process conditions while preserving the power savings of the 5T architecture
Solution Approach 2:
The patent employs dynamic transistor sizing and threshold voltage adjustment to adapt the access transistor's behavior to process variations. This dynamic optimization ensures read stability across different manufacturing conditions while maintaining the lower power consumption characteristic of the 5T structure
4Ease of operation
If access transistor size is increased, then writeability is improved, but layout size increases
Solution Approach 1:
The patent optimizes the width-to-length ratio parameter of the single access transistor to achieve proper writeability. By adjusting this geometric parameter, the access transistor gains sufficient drive strength for writing operations without requiring a proportional increase in overall cell area, thus improving writeability while minimizing layout size expansion
Data Source
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AI summary
A 5 Transistor Static Random Access Memory (5T SRAM) is designed for reduced cell size and immunity to process variation. The 5T SRAM (400) includes a storage element (402) for storing data, wherein the storage element is coupled a first voltage and a ground voltage. The storage element can include symmetrically sized cross - coupled inverters. A single access transistor (M5 ) controls read and write operations on the storage element (402). Control logic (M6,M6') is configured to generate a value of the first voltage for a write operation that is different from the value of the first voltage for a read operation.