60 GHz OFDM LDPC Coding With Sub-Carrier Interleaving
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Solution Overview
Problem
Current communication systems using LDPC codes face challenges in achieving low bit error rates at high data rates due to latency constraints and the need to approach Shannon's limit, particularly in wireless and high-speed Ethernet applications.
Innovation Solution
The development of novel LDPC code constructions with partial tree-like structures and specific parity check matrices, including CSI sub-matrices, to enhance decoding performance and reduce error floors, allowing for efficient sub-carrier interleaving and modulation in communication systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional concatenated codes are used to achieve low bit error rates, then reliability is improved, but latency increases making them unsuitable for high data rate applications
Solution Approach 1:
The patent changes the fundamental parameters of the coding structure by using LDPC codes with specific parity check matrices and tree-like structures, achieving both low bit error rates and low latency simultaneously, unlike traditional concatenated codes that require multiple encoding/decoding stages causing latency
Solution Approach 2:
The patent segments the code structure into specific components including tree-like structures and carefully designed parity check matrices that enable efficient decoding algorithms, achieving high performance without the latency of traditional concatenated approaches
2Reliability
If LDPC codes with longer lengths are used to approach Shannon's limit, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent optimizes specific parameters of the LDPC code including the parity check matrix structure and code length to achieve near-Shannon-limit performance with reduced hardware complexity through efficient encoding and decoding algorithms
Solution Approach 2:
The patent applies local quality by using specific tree-like structures and CSI sub-matrices in particular positions of the parity check matrix to achieve high reliability without requiring uniformly complex structures throughout the entire code
3Reliability
If conventional error correction codes are used to ensure low bit error rates, then reliability is improved, but the system cannot achieve high data rates due to latency constraints
Solution Approach 1:
The patent changes the coding parameters and structure to enable operation at high data rates by reducing latency while maintaining low bit error rates, making the system suitable for high-speed Ethernet and wireless applications
Data Source
AI summary
LDPC coding systems for 60 GHz millimeter wave based physical layer extension. LDPC (Low Density Parity Check) encoding in cooperation with sub-carrier interleaving, in the context of orthogonal frequency division multiplexing (OFDM), and appropriate symbol mapping is performed in accordance with transmit processing as may be performed within a communication device. In a receiving communication device, receive processing may be performed on a received signal based on the type of LDPC, sub-carrier interleaving, and symbol mapping thereof. The LDPC code employed in accordance with such LDPC encoding may have a partial-tree like structure. In addition, appropriate manipulation of the bits assigned to respective sub-carriers may be performed to ensure that the bits emplaced in the MSB (Most Significant Bit) location of various symbols has some desired diversity (e.g., from different codewords, from appropriately different locations within a given codeword, etc.).