60GHz Power Amplifier Interconnect Layout for Gain Recovery
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Solution Overview
Problem
Conventional high-frequency circuit design techniques introduce unnecessary resistive losses, particularly between the pre-driver and final output stage of transmitters, which hinder achieving desired gain parameters at 60 GHz frequencies, leading to potential chip failure in meeting specifications.
Innovation Solution
The solution involves removing significant resistance in the coupling path between the pre-drive and final output stage by eliminating two via stacks, which reduces contact resistance and increasing gain by 2 dB, and using cross-coupled devices in the power amplifier to reduce common mode oscillations and compensate for resistive losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional physical layout techniques are used in high frequency circuit design, then circuit integration is achieved, but unnecessary resistive losses are introduced
Solution Approach 1:
The patent extracts and removes the harmful via stacks from the coupling path between the pre-driver and final output stage. By eliminating these unnecessary via connections, the design removes the source of resistive losses while maintaining the integrated circuit structure, directly resolving the contradiction between integration and energy loss.
Solution Approach 2:
The patent applies different quality requirements to different parts of the circuit. The coupling path between pre-driver and final output stage is given special attention with optimized metal routing and minimal via connections, while other parts of the circuit maintain standard integration. This local optimization reduces resistive losses in the critical path without compromising overall integration.
2Ease of operation
If via stacks are used to interconnect devices in the coupling path, then vertical connectivity is achieved, but contact resistance increases significantly
Solution Approach 1:
The patent removes two via stacks from the coupling path between the pre-driver drain and the final output stage gate. Each via stack can introduce up to 8 series contact resistances, and their elimination directly reduces contact resistance and energy loss while maintaining necessary connectivity through alternative metal layer routing.
Solution Approach 2:
Instead of using vertical via connections, the patent transitions to horizontal routing through metal layers. The coupling path is reconfigured to use metal interconnects that traverse the circuit plane laterally rather than vertically through via stacks, thereby eliminating contact resistance associated with via connections while maintaining electrical connectivity.
3Device complexity
If standard metal interconnects are used between pre-driver and final output stage, then routing is simplified, but gain is reduced due to resistive losses
Solution Approach 1:
The patent applies enhanced routing quality specifically to the coupling path between pre-driver and final output stage. This critical path uses optimized metal routing with minimal via connections and reduced resistance, while other parts of the circuit use standard routing. The local quality enhancement in the gain-critical path directly improves transmitter gain without significantly increasing overall routing complexity.
Solution Approach 2:
The patent changes the electrical parameters of the coupling path by reducing resistance through optimized metal routing and eliminating via stacks. This parameter change directly increases the gain of the transmitter stage by 2 dB, as the reduced resistive losses allow more signal power to be transmitted through the coupling path.
Data Source
AI summary
Very high frequency circuits suffer from parasitic resistances. At 60 GHz, conventional layout techniques can introduce loss into the circuit at critical locations. One critical interconnect between the output of a pre-driver and the gate of the final output stage causes 1 or 2 dB of loss due to the layout. By minimizing the number of via contacts, this conventional loss can be recovered using this new layout technique. In addition, a tap point of a via stack is used to modify the resonant characteristics of the interconnect. Finally, cross coupled devices in a resonant circuit are used to reduce the common mode noise at the expense of the common mode gain.