LDPC Bit Interleaving Scheme for 64800-Bit 4096-Symbol BICM
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver optimized for an LDPC coder with a length of 64800 and code rate of 3/15, using 4096-symbol mapping, which interleaves the LDPC codeword on a bit group basis with a parallel factor of 360, effectively distributing burst errors through a specific permutation order.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional bit interleaver is used in BICM systems, then the system structure remains simple, but burst errors in the channel cause rapid performance degradation
Solution Approach 1:
The patent divides the 64800-bit LDPC codeword into 180 bit groups of 360 bits each, applying segmentation to enable optimized interleaving. This segmentation allows the system to handle burst errors more effectively by distributing them across different bit groups while maintaining a manageable interleaver structure that doesn't excessively increase complexity
Solution Approach 2:
The patent applies specific parameter changes by optimizing the interleaver for particular LDPC coder parameters (length 64800, code rate 3/15) and modulation schemes (4096-symbol QAM). This targeted parameter optimization improves reliability for specific configurations without requiring a completely complex universal design
2Reliability
If the bit interleaver is optimized for specific LDPC coder parameters and modulation schemes, then performance reliability improves, but the adaptability to different configurations decreases
Solution Approach 1:
The patent optimizes the interleaver for specific parameters (LDPC length 64800, code rate 3/15, 4096-QAM modulation) to achieve superior error correction performance. This specialized optimization sacrifices some adaptability to different configurations but delivers reliable performance for the target application in next-generation broadcasting systems
3Reliability
If burst errors are distributed through optimized interleaving, then performance degradation is prevented, but the computational complexity of the interleaving process increases
Solution Approach 1:
By segmenting the codeword into 180 bit groups of 360 bits each, the patent enables effective burst error distribution while keeping the interleaving computation manageable. The segmented structure allows for systematic interleaving that prevents performance degradation without requiring excessively complex computational processes
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.