64B/66B-Compatible FEC Coding for Scrambling-Induced Bit Errors
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Solution Overview
Problem
High-speed digital communication systems face challenges in correcting single bit errors that are multiplied due to self-synchronized scrambling, leading to bit error spreading, which can exceed the capability of existing error correction codes, especially in multi-channel communication systems.
Innovation Solution
A Forward Error Correction (FEC) code compatible with the 64B/66B scrambling standard is developed, combining a Hamming code with a Bit Interleaved Parity code of degree n, allowing encoding and decoding before and after scrambling to correct single transmission errors multiplied by the 64B/66B scrambling process, and ensuring unique error syndromes for all single and replicated bit errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If self-synchronized scrambling is used to maintain clock synchronization, then synchronization reliability is improved, but single bit errors are multiplied causing bit error spreading
Solution Approach 1:
The patent segments the error correction task into two distinct parts: a first error correction code handles errors in the data portion, while a second error correction code handles errors in the encoded portion. This segmentation allows each code to be optimized for its specific function, preventing error spreading from affecting the entire block uniformly.
Solution Approach 2:
The patent introduces an intermediary structure by separating the data and encoded portions with distinct error correction mechanisms. This intermediary approach allows the system to handle scrambling-induced errors without requiring the entire block to be retransmitted, thus mitigating the harmful effect of bit error spreading.
2Reliability
If error correction checkbits are appended to dataword, then error correction capability is improved, but bit transition density requirements become more difficult to maintain
Solution Approach 1:
The patent divides the error correction checkbits into two separate groups: first checkbits appended to the data portion and second checkbits appended to the encoded portion. This segmentation allows each group to be processed independently, maintaining bit transition density requirements for each segment without compromising overall error correction capability.
Solution Approach 2:
The patent applies different error correction strategies to different portions of the data block. The first error correction code is applied locally to the data portion, while the second error correction code is applied locally to the encoded portion. This local quality approach allows each portion to maintain its specific bit transition density requirements while achieving comprehensive error correction.
3Productivity
If multiple serial links are used to transmit data, then transmission bandwidth is improved, but error correction complexity increases due to distributed errors
Solution Approach 1:
The patent segments the error correction function into two distinct codes that operate on different portions of the transmitted data. This segmentation allows the system to handle errors distributed across multiple serial links more efficiently, as each error correction code can independently process its designated portion without requiring complex coordination between links.
Data Source
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AI summary
A Forward Error Correction (FEC) code compatible with the self-synchronized scrambler used by the 64B/66B encoding standard for transmission on Serializer/Deserializer (SerDes) communications channel links. The FEC code allows encoding and decoding to occur before and after scrambling, respectively, so as to preserve the properties of the scrambling operation on the transmitted signal. The code allows the correction of any single transmission error in spite of the multiplication by three of all transmission errors due to the 64B/66B scrambling process. A Hamming code is combined with a Bit Interleaved Parity code of degree n (BIP-n). These two codes provide for protection both for an error anywhere in the maximum length of the packet as well as for an error replicated two or three times by the descrambling process. All single bit errors, whether multiplied or not, have unique syndromes and are therefore easily correctable. In addition, the packet can be transported across multiple serial links for higher bandwidth applications without a degradation of the code efficiency. The Hamming code can be generated from any irreducible polynomial, such as H(x) = x10 + x3 + 1. The BIP code is chosen to be of degree 6 to fit with 64B/66B scrambling polynomial and is represented by B(x) = x6 + 1.