64B/66B Encoding Circuit for Idle-Free Packet Data Transfer
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Solution Overview
Problem
The existing 64B/66B encoding data generation methods suffer from reduced packet data transfer efficiency due to the inclusion of idle data, particularly in patterns PTN2 and PTN3, which deteriorates the overall data transfer efficiency to the 64B/66B encoding circuit.
Innovation Solution
A method and circuit that generate user data with head and tail identifying bytes based on received packet data and information, writing and reading this data in a memory to provide it to the 64B/66B encoding circuit, allowing for efficient data patterns like PTN3 and generating maintenance data to replace idle periods, ensuring compliance with the 64B/66B encoding rule.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If idle data is included in user data generation (patterns PTN2 and PTN3), then the 64B/66B encoding rule is satisfied, but packet data transfer efficiency deteriorates
Solution Approach 1:
The patent extracts and removes idle data from the user data stream by implementing a judgment mechanism that identifies and eliminates unnecessary idle bytes before 64B/66B encoding, thereby improving transfer efficiency while maintaining encoding rule compliance through alternative data patterns
Solution Approach 2:
The patent dynamically adjusts user data patterns based on packet data reception states, transitioning between different patterns (PTN3, PTN4, PTN12) to optimize data transfer efficiency while ensuring 64B/66B encoding rule compliance through state-dependent pattern selection
2Reliability
If multiple data patterns (PTN1-PTN12) are used to handle different reception states, then encoding rule compliance is maintained, but device complexity increases
Solution Approach 1:
The patent segments the data generation process into distinct modules: packet data reception state judgment unit, user data generation unit, and 64B/66B encoding unit, each handling specific functions to manage complexity while ensuring encoding compliance across different patterns
Solution Approach 2:
The patent implements a universal data generation circuit that can produce multiple data patterns (PTN3, PTN4, PTN12) using the same hardware structure, allowing the system to adapt to different reception states without requiring separate dedicated circuits for each pattern
Data Source
AI summary
In a more effective data generation method and circuit used for 64B/66B encoding, when packet data, and head and tail information of the data packet are received, write user data in which a head and tail identifying bytes are respectively added to a head and a tail of the packet data based on the head and tail information is associated with control data indicating positions of both of the identifying bytes to be written in a memory sequentially from a predetermined address of the memory. From the predetermined address, user data by 8 bytes and the control data corresponding to the user data are sequentially read to be provided to a 64B/66B encoding circuit. During a period in which the reading can not be made, idle bytes for 8n bytes (n≧1) and control data indicating the idle bytes, or maintenance user data of 8n bytes (n≧2) in which the head and tail identifying bytes are respectively added to a head and a tail of the maintenance information and control data indicating positions of both of the identifying bytes are provided to the 64B/66B encoding circuit.