6F2 Semiconductor Layout with Triangular Junctions
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Solution Overview
Problem
The 6F2 layout for semiconductor integrated circuit devices faces challenges in enhancing productivity due to structural weaknesses and close tolerances, which hinder the increase in integration density and yield.
Innovation Solution
The semiconductor integrated circuit device incorporates a substrate with unit active regions, first and second access transistors, junction areas, bitlines, and bitline contacts that directly connect the first junction area and bitlines, utilizing epitaxial layers to prevent metal silicide encroachment and reduce leakage current, while simplifying manufacturing through shared masks for junction areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 6F2 layout is used to reduce memory cell size, then integration density is improved, but manufacturing precision and productivity deteriorate due to structural weakness and close tolerances
Solution Approach 1:
The patent changes the geometric parameters of the memory cell structure by introducing triangular-shaped junction areas and strategically positioned bitline contacts. This parameter change allows the cell to maintain 6F2 density while improving manufacturability through more tolerant contact placement and reduced sensitivity to dimensional variations
Solution Approach 2:
The patent introduces triangular junction areas as intermediary structures between the gate lines and bitlines. These triangular regions serve as buffer zones that accommodate manufacturing tolerances and reduce the direct stress between closely spaced components, thereby improving yield while maintaining high density
2Quantity of substance
If 6F2 layout is used to reduce memory cell size, then integration density is improved, but reliability deteriorates due to 2-bit failures and leakage current
Solution Approach 1:
The patent applies local quality by creating triangular junction areas with specific doping characteristics positioned at critical locations. These localized regions have enhanced electrical properties that prevent leakage current and reduce the probability of 2-bit failures, while the overall cell size remains minimized for high density
3Quantity of substance
If bitline contacts are positioned closely to reduce cell area, then integration density is improved, but manufacturing precision deteriorates due to encroachment and alignment difficulty
Solution Approach 1:
The patent performs preliminary action by pre-defining triangular junction areas before forming the bitline contacts. This preliminary structuring creates predetermined zones that guide subsequent contact formation, ensuring proper positioning and reducing alignment errors even when contacts are placed closely together for high density
Data Source
AI summary
A semiconductor integrated circuit device having a 6F2 layout is provided. The semiconductor integrated circuit device includes a substrate; a plurality of unit active regions disposed in the substrate and extending in a first direction; first and second access transistors including first and second gate lines disposed on the substrate and extending across the unit active regions in a second direction forming an acute angle with the first direction; a first junction area disposed in the substrate between the first and second gate lines and second junction areas disposed on sides of the first and second gate lines where the first junction area is not disposed; a plurality of bitlines disposed on the substrate and extending in a third direction forming an acute angle with the first direction; and a plurality of bitline contacts directly connecting the first junction area and the bitlines.