7-T SRAM Cell with Separate Read and Write Ports
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Solution Overview
Problem
Conventional dual-port SRAM cells have a write disturb problem and a large cell size due to the number of transistors required, which limits their efficiency and integration in memory devices.
Innovation Solution
A 7-T SRAM cell design with separate read and write ports, utilizing PMOS and NMOS transistors to minimize cell size while maintaining dual-port functionality, where the write and read paths have distinct addressing word-lines and bit-lines, allowing simultaneous read and write operations without disturbing other cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional 8-T dual port SRAM cell is used to provide separate read and write ports, then dual-port functionality is achieved, but the cell size becomes large due to eight transistors and additional read-port word-line and bit-line
Solution Approach 1:
The patent merges the read and write ports into a unified 6-T SRAM cell structure, sharing common storage nodes (C and D), cross-coupled inverters, and bit-line connections. This integration eliminates the need for separate read-port transistors and additional word-lines, reducing cell size while maintaining dual-port functionality through selective activation of read or write operations
Solution Approach 2:
The patent makes the 6-T SRAM cell structure universal by enabling it to perform both read and write operations through the same physical components. The cross-coupled inverters and pass-gate transistors serve multiple functions: storing data, enabling read operations, and enabling write operations, depending on the control signals applied to the word-line and bit-lines
2Productivity
If a conventional 8-T dual port SRAM cell is used with all pass-gate transistors turned on during write cycle, then write operation is enabled, but write disturb problem occurs for cells on the same word-line exposing storage nodes
Solution Approach 1:
The patent segments the write operation control by introducing separate word-line (WL) and write-enable (WE) control signals that independently manage different aspects of the write process. The WL selects the target cell while WE controls the actual write data transfer, allowing precise control that prevents unintended disturbance of other cells on the same word-line
Solution Approach 2:
The patent introduces the write-enable (WE) signal as an intermediary control mechanism between the word-line selection and the actual write operation. This intermediary ensures that write data is only transferred to the selected cell when WE is activated, preventing harmful write disturb effects on neighboring cells that share the same word-line
Data Source
AI summary
This invention discloses a dual port static random access memory (SRAM) cell, which comprises at least one inverter coupled between a positive supply voltage (Vcc) and a complementary low supply voltage (Vss) and having an input and an output terminals, at least one PMOS transistor with its gate, source and drain connected to the output terminal, Vcc and input terminal, respectively, a write port connected to the input terminal and having a write-word-line, a write-enable and a write-bit-line, and a read port connected to either the input or output terminal and having a read-word-line and a read-bit-line.