7T-LSRAM Bitcell Dynamic Feedback for Low-Voltage Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Designing ultra-low-power SRAM for nanoscale CMOS technology is challenging due to reduced static noise margin and increased variability in design and process parameters, leading to instability and poor yield, especially at ultra-low voltage operations.
Innovation Solution
A 7-transistor Latch-Style Static Random Access Memory (7T-LSRAM) bitcell structure is proposed, featuring a pair of inverters with a cross-coupling path and a transmission gate comprising PMOS and NMOS transistors, which allows for selective disconnection and reconnection of the feedback loop during read and write operations, improving stability and write-ability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If supply voltage is reduced to reduce power consumption, then energy consumption is reduced, but static noise margin is reduced and stability is worsened
Solution Approach 1:
The patent introduces a transmission gate that dynamically controls the coupling between cross-coupled inverters based on operational phase. During write operations, the transmission gate is activated to enable strong coupling for stable data retention. During read operations, the transmission gate is deactivated to allow bit-line connection while maintaining sufficient noise margin through controlled coupling strength. This dynamic reconfiguration enables the SRAM cell to maintain reliability across different operational modes at reduced supply voltages.
Solution Approach 2:
The patent modifies the coupling strength parameter between cross-coupled inverters by introducing a controllable transmission gate. This allows the noise margin parameter to be adjusted dynamically - stronger coupling during write/hold phases for stability, and optimized coupling during read phases for bit-line sensing. The transmission gate's on-resistance serves as a可调 parameter to optimize the balance between noise margin and operational functionality at ultra-low voltages.
2Use of energy by moving object
If supply voltage is reduced to reduce power consumption, then energy consumption is reduced, but write-ability is worsened
Solution Approach 1:
The transmission gate provides dynamic control over the feedback path strength during write operations. By temporarily activating the transmission gate during write phases, the patent ensures strong coupling between inverters to maintain stability while the write operation progresses. The gate can be deactivated during critical sensing phases to allow bit-line voltage to dominate for successful write. This temporal separation of coupling strengths enables reliable write operations at reduced voltages where static coupling would be insufficient.
3Loss of energy
If supply voltage is reduced to reduce power consumption, then leakage power is reduced, but process parameter variability sensitivity is increased
Solution Approach 1:
The transmission gate introduces a controllable resistance parameter that can compensate for process variations. By adjusting the gate's coupling strength, the patent can optimize the balance between cross-coupled inverter strength and bit-line loading for each process corner. The gate's on-resistance serves as a tuning parameter that can be designed to provide sufficient noise margin across process variations, effectively decoupling the sensitivity to manufacturing precision from the supply voltage reduction.
4Reliability
If cross-coupling is strengthened to improve stability, then static noise margin is improved, but write-ability is worsened
Solution Approach 1:
The transmission gate enables temporal separation of coupling strengths - strong coupling during hold/write phases for stability, and reduced coupling during read phases for write-ability. By controlling the gate's activation timing, the patent achieves both strong static noise margin when needed and sufficient write-ability when bit-line connection is required, resolving the fundamental trade-off between these two opposing requirements.
Data Source
AI summary
A static random access memory (“SRAM”) comprising: a pair of inverters each having an input and an output; a cross-coupling path coupling the input of a first inverter to the output of a second inverter; and a transmission gate, wherein the transmission gate comprises a p-channel transistor coupling the input of the second inverter to the output of the first inverter; and an n-channel transistor coupling the input of the second inverter to the output of the first inverter in parallel with the p-channel transistor. In another embodiment, the SRAM comprises a first inverter having a supply voltage node connected to a supply voltage, and a ground node connected to ground; a second inverter cross-coupled with the first inverter and having a supply voltage node connected to a supply voltage, and a ground node; and a switch selectively connecting and disconnecting the ground node of the second inverter to ground.