7T SRAM Cell Read Stability via Segmented Access
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Solution Overview
Problem
Conventional six-transistor (6T) static random access memory (SRAM) cells face limitations in READ stability and half-select stability due to increased process variations and random mismatch, leading to lower stability compared to past technologies, with existing solutions either increasing area or power consumption.
Innovation Solution
A single-ended seven-transistor (7T) SRAM cell design that uses a first and second supply voltage, eliminating the need for a complementary WRITE bit line, with a WRITE access device and series READ access devices to improve READ stability and reduce area and power requirements, while allowing writing of logical 'one' with a higher WRITE word line voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional 6T SRAM cell is used, then area is minimized, but READ stability and half-select stability deteriorate due to process variations
Solution Approach 1:
The access path is segmented into two series-connected NFETs (N1, N2) for READ operations, while the WRITE path uses a single NFET (SL). This segmentation allows the READ access devices to provide sufficient off-state current to ground the READ bit line while maintaining stability, resolving the contradiction between READ stability and area by optimizing the transistor configuration rather than simply adding more transistors.
Solution Approach 2:
Different transistor types and configurations are used in different parts of the cell: PFETs (PL, PR) are used for pull-up devices in inverters, while NFETs (N1, N2, SL) are used for access devices. The series-connected NFETs N1 and N2 have specific threshold voltage characteristics optimized for READ stability. This local differentiation of device properties allows the cell to achieve improved READ stability without proportionally increasing area.
2Reliability
If prior-art 8T SRAM cell is used, then READ stability is improved, but area increases due to extra transistors and bit lines
Solution Approach 1:
The complementary WRITE bit line and its associated SR access device are extracted/removed from the cell structure. The invention achieves WRITE functionality using a single WRITE bit line (WBL) and a single NFET access device (SL), eliminating the need for the complementary WRITE infrastructure. This reduction in complexity and component count directly reduces cell area while maintaining READ stability through the series-connected N1-N2 access devices.
Solution Approach 2:
The single WRITE bit line WBL serves multiple functions: it enables WRITE operations through the SL access device and can be shared across multiple cells. The series-connected N1-N2 pair serves dual purposes: they provide READ access stability while also contributing to the overall cell logic functionality. This multi-functionality reduces the total component count compared to the 8T cell.
3Reliability
If process variations are reduced, then stability improves, but manufacturing complexity increases
Solution Approach 1:
The invention employs specific threshold voltage parameters for different transistors to achieve stability without requiring reduced process variations. The PFETs (PL, PR) and NFETs (N1, N2, SL) are designed with threshold voltages optimized for their specific functions. By carefully selecting and designing transistor parameters during manufacturing, the cell achieves improved half-select stability using standard manufacturing processes without requiring additional process steps or reduced variation.
Data Source
AI summary
A memory cell for interconnection with READ and WRITE word lines and READ and WRITE bit lines includes a logical storage element such as a flip-flop formed by a first inverter and a second inverter cross-coupled to the first inverter. The storage element has first and second terminals and a storage element supply voltage terminal configured for interconnection with a first supply voltage. A WRITE access device is configured to selectively interconnect the first terminal to the WRITE bit line under control of the WRITE word line, and a pair of series READ access devices are configured to ground the READ bit line when the READ word line is active and the second terminal is at a high logical level. A logical “one” can be written to the storage element when a second supply voltage, greater than the first supply voltage, is applied to the WRITE word line, substantially without the use of a complementary WRITE bit line.