7T1R SRAM Cell with Resistive Element for Non-Volatile Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional SRAM cells face challenges in reducing power consumption and improving write-margin while maintaining non-volatility, as they require high power for refresh operations and have limited integrability due to their structure.
Innovation Solution
A 7T1R non-volatile static random access memory cell is introduced, comprising a first and second inverter, access transistors, and a variable resistive element, operating in a dual supply initialization and pulse-overwrite phase to reduce power consumption and enhance write-margin, with the addition of a third access transistor and variable resistive element in series.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional 6T SRAM cell structure is used, then high speed operation and low power consumption are achieved, but non-volatility cannot be maintained and power consumption increases due to refresh operations
Solution Approach 1:
The patent merges the volatile SRAM cell structure with a non-volatile resistive memory element (RRAM) by adding a variable resistive element and third access transistor in series with the existing 6T SRAM structure. This combination allows the cell to maintain data without power while preserving SRAM's high-speed operation, resolving the contradiction between non-volatility and power consumption.
Solution Approach 2:
The 7T1R cell structure performs multiple functions: the SRAM portion handles high-speed read/write operations while the RRAM portion provides non-volatile storage. The cell can operate in both volatile SRAM mode for speed-critical applications and non-volatile memory mode for power-saving applications, making it universally applicable to different scenarios.
2Ease of manufacture
If conventional 6T SRAM cell structure is used, then high integrability is achieved, but write-margin is limited and power consumption increases
Solution Approach 1:
The patent changes the electrical parameters of the cell by introducing a variable resistive element that can switch between high and low resistance states. This parameter change enables the cell to achieve better write-margin by controlling the current flow through the resistive element during write operations, while maintaining high integrability through the standardized transistor and resistor implementation.
3Use of energy by moving object
If additional components are added to achieve non-volatility, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent segments the memory cell into two functional parts: a 6T SRAM core for high-speed operations and a separate RRAM element with an additional transistor for non-volatile storage. This segmentation allows each component to be optimized independently - the SRAM part remains simple and fast, while the RRAM part provides non-volatility with minimal added complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 7T1R SRAM cell reduces power consumption, increases restore yield, and improves write-margin, while also saving energy and circuit area compared to previous non-volatile SRAM designs.
Implementation Method 1
a variable resistive element coupling with a third access transistor in series is coupled to the first output node
Data Source
AI summary
A non-volatile SRAM cell comprises a first inverter, a second inverter, a first access transistor, a second access transistor, and a variable resistive element. The first inverter voltage is supplied by a first differential supply. The second inverter voltage is supplied by a second differential supply. The variable resistive element coupling with a third access transistor in series is coupled to the first output node. The non-volatile SRAM cell operates in a restore operation comprising a dual supply initialization phase and a pulse-overwrite phase. During the dual supply initialization phase, the first differential supply increases before the second differential supply so as to initialize the first output node to a logic state. During the pulse-overwrite phase, the third access transistor is turned on for a switch period in order to discharge/charge the first output node.