8b/9b Bus Encoding for Two-Aggressor Crosstalk Elimination
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Solution Overview
Problem
High speed parallel bus architectures face signal integrity issues such as crosstalk, inter-symbol interference, and simultaneous switching output noise, which existing solutions like Data Bus Inversion (DBI) do not adequately address, and are costly to implement due to the need for additional circuit elements or design modifications.
Innovation Solution
An 8b/9b encoding scheme that maps eight-bit data words to nine-bit code words, where each valid code word does not have three consecutive logic-high bits, reducing crosstalk by controlling bit transitions on the parallel bus, thereby eliminating two-aggressor crosstalk while allowing one-aggressor crosstalk to maintain signal integrity at higher clock frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If Data Bus Inversion (DBI) encoding is used to reduce signal integrity issues, then power consumption is reduced by minimizing low-level line drivers, but crosstalk is not adequately addressed and the solution becomes prohibitive when additional circuit elements are required
Solution Approach 1:
The patent changes the encoding parameters by using an 8b/9b transition-based encoding scheme that controls the number of logic transitions rather than simply inverting bits. This approach addresses crosstalk by limiting simultaneous transitions on adjacent lines while maintaining reasonable power consumption characteristics.
Solution Approach 2:
The patent segments the data bus into individual transmission lines and applies transition control independently to each line based on its adjacent lines' states. This segmentation allows targeted reduction of crosstalk between specific adjacent lines without requiring global circuit modifications.
2Object-affected harmful factors
If physical layout modifications are made to reduce crosstalk (increasing spacing or adding ground traces), then crosstalk is reduced, but device expense and complexity increase
Solution Approach 1:
The patent replaces physical/layout-based crosstalk reduction mechanisms with a logical/encoding-based approach. Instead of modifying physical trace spacing or adding ground traces, the solution uses transition-based encoding to control signal transitions, eliminating the need for additional physical circuit elements.
Solution Approach 2:
The patent uses a simple encoding/decoding logic that can be implemented with minimal circuit elements, replacing expensive physical layout modifications. The encoding scheme itself acts as a low-cost virtual barrier against crosstalk without requiring additional hardware resources.
3Reliability
If trace spacing is increased or ground traces are added to reduce crosstalk, then signal integrity improves, but the physical design becomes prohibitive due to size restrictions
Solution Approach 1:
The patent moves the crosstalk reduction problem from the spatial domain (physical layout) to the temporal/domain coding dimension. By controlling when transitions occur through encoding rather than how closely lines are spaced physically, the solution maintains signal integrity without increasing the physical bus area.
4Loss of energy
If conventional encoding techniques like DBI are used, then power consumption is reduced, but they do not adequately address crosstalk interference
Solution Approach 1:
The patent creates a composite encoding approach that combines elements of transition control and data encoding. The 8b/9b encoding scheme integrates transition management with data representation, simultaneously addressing both power consumption and crosstalk interference that conventional separate approaches could not handle together.
Data Source
AI summary
Systems and methods for encoding/decoding a data word using an 8b/9b encoding scheme that eliminates two-aggressor crosstalk are disclosed. The 8b/9b encoding scheme enables a data word to be encoded using code words. Each of the valid code words does not include any three consecutive bits having a logic level of logic-high (i.e., ‘1’), and represent transition vectors for consecutive symbols transmitted over the high speed parallel bus. An encoder and corresponding decoder are disclosed for implementing the 8b/9b encoding scheme. In one embodiment, the encoder/decoder implements a modified Fibonacci sequence algorithm. In another embodiment, the encoder/decoder implements a look-up table.