8K Display Using 4K ASIC Segmentation and Temporal Multiplexing
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Solution Overview
Problem
Current 8K display products rely on expensive field-programmable gate arrays (FPGAs) for image data processing, necessitating a cost-effective alternative for displaying 8K-resolution images using ASIC chips in 4K or 2K resolutions.
Innovation Solution
A display apparatus and method utilizing a solution-on-chip (SOC) with a central processing unit (CPU) to divide 8K-resolution image data into four parts, processed by an FPGA for reconstruction and displayed on a panel, leveraging a timing controller and external memory to achieve efficient data transfer and display.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an FPGA is used to process 8K image data, then image processing capability is improved, but device cost increases
Solution Approach 1:
The patent divides an 8K resolution frame into four separate 4K resolution frames. This segmentation allows a 4K ASIC chip to process each subdivided frame independently, achieving 8K display capability through temporal multiplexing while using a lower-cost 4K processor instead of an expensive 8K-capable FPGA.
Solution Approach 2:
The patent changes the resolution parameter from 8K to 4K for the processing chip, and compensates by increasing the frame rate. The 4K ASIC chip processes four frames per second at 4K resolution, which when combined through the display panel's pixel arrangement, achieves effective 8K resolution display.
2Ease of manufacture
If a 4K ASIC chip is used instead of 8K FPGA, then device cost is reduced, but image processing capability deteriorates
Solution Approach 1:
The patent segments the 8K frame into four 4K frames that are processed sequentially by the 4K ASIC chip. By dividing the high-resolution frame into multiple lower-resolution frames and processing them in sequence, the system achieves 8K output capability using a 4K-capable processor.
Solution Approach 2:
The patent employs periodic action by processing four 4K frames in sequence to represent one 8K frame. The display panel refreshes at a higher frame rate, cycling through the four processed frames to reconstruct the 8K image, thereby achieving high-resolution display with a lower-cost processor.
3Productivity
If 8K image data is divided into four parts, then data processing load is reduced, but device complexity increases
Solution Approach 1:
The patent segments the 8K frame data into four separate 4K frame data sets, which are then processed by the 4K ASIC chip. This segmentation reduces the processing burden on each individual frame while maintaining the overall 8K resolution through temporal multiplexing and display panel reconstruction.
Data Source
AI summary
The present application discloses a display apparatus including a solution-on-chip (SOC) comprising a first input port receiving video data, a second input port configured to receive image data in a first resolution, and a central-processing unit comprising a frame-cut block integrated with an image processor to divide a frame of image data in the first resolution to 4 parts of the frame in a second resolution in a serial order. The display apparatus further includes a FPGA configured to write, read, and process respective one of the 4 parts of the frame in the serial order sent from the SOC to reconstruct a frame of image data in the first resolution. Furthermore, the display apparatus includes a TCON configured to receive the frame of the image data in the first resolution reconstructed by the FPGA and a display panel driven by the TCON to display the frame of image data.